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John T Pedicone

from New Smyrna Beach, FL
Age ~67

John Pedicone Phones & Addresses

  • New Smyrna Beach, FL
  • 10344 Newington Dr, Orlando, FL 32836 (407) 327-1913
  • 308 Twelve Oaks Dr, Winter Springs, FL 32708 (407) 327-1913
  • 388 Twelve Oaks Dr, Winter Springs, FL 32708 (407) 327-1913
  • 388 Twelve Oaks Dr #12, Winter Springs, FL 32708 (407) 327-1913
  • 1032 Chatham Pines Cir #20, Winter Springs, FL 32708 (407) 327-1913
  • 1989 Summer Club Dr #107, Oviedo, FL 32765 (407) 365-9491
  • 1989 Summer Club Dr, Oviedo, FL 32765
  • Niskayuna, NY
  • Yorktown Heights, NY
  • Brookfield, WI
  • 10344 Newington Dr, Orlando, FL 32836

Work

Position: Clerical/White Collar

Education

Degree: Graduate or professional degree

Resumes

Resumes

John Pedicone Photo 1

Staff Consultant

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Location:
Orlando, FL
Industry:
Semiconductors
Work:
Real-3D 1995 - 1997
Computer Engineer

Ge Global Research Sep 1983 - Sep 1993
Computer Systems Engineer

Synopsys Sep 1983 - Sep 1993
Staff Consultant
Education:
Rensselaer Polytechnic Institute 1982 - 1983
Master of Science, Masters, Computer Engineering
University at Albany, Suny 1976 - 1980
Bachelors, Bachelor of Arts, Psychology
Skills:
Eda
Asic
Semiconductors
Static Timing Analysis
Soc
Timing Closure
Verilog
Physical Design
Vlsi
Perl
Integrated Circuit Design
Debugging
Tcl
Rtl Design
Ic
John Pedicone Photo 2

John Pedicone

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John Pedicone Photo 3

John Pedicone

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Publications

Us Patents

State Machine Controller Capable Of Producing Result Per Clock Cycle Using Wait/No Wait And Empty Signals To Control The Advancing Of Data In Pipeline

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US Patent:
60444576, Mar 28, 2000
Filed:
Apr 3, 1998
Appl. No.:
9/054820
Inventors:
Michael Mantor - Orlando FL
John Pedicone - Winter Springs FL
Steven Manno - Ormond Beach FL
Val Gene Cook - Shingle Springs CA
Assignee:
Real 3D, Inc. - Orlando FL
International Classification:
G06F 1300
US Classification:
712223
Abstract:
A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The state machine controller can produce a result per clock pulse, schedule new data to be processed before completion of the processing of previous data to prevent bubbles or interruptions in the data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, and can resume one clock operation on the clock pulse when the hold is removed.

Content Addressable Memory Fifo With And Without Purging

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US Patent:
60527579, Apr 18, 2000
Filed:
Dec 18, 1997
Appl. No.:
8/993513
Inventors:
John Thomas Pedicone - Winter Springs FL
Thomas Andrew Chiacchira - Orlando FL
Andres Alvarez - Orlando FL
Assignee:
Real 3D, Inc. - Orlando FL
International Classification:
G06F 1200
US Classification:
711108
Abstract:
A content-addressable, first-in/first-out memory (CAM-FIFO), as used to provide a read-modify-write buffer for data between two processes, includes: a Content Addressable Memory (CAM) which stores flag data; a FIFO memory portion for providing data storage; a write/read address counting section for providing write/read addresses of data to be stored in/read from the FIFO; and logic to determine and is used to query data on the queue to determine if the FIFO data should still be sent to the receiving process, or replaced with at least part of the flag data.

Acoustic Composite Material For An Ultrasonic Phased Array

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US Patent:
56541015, Aug 5, 1997
Filed:
Apr 15, 1996
Appl. No.:
8/636728
Inventors:
Peter William Lorraine - Niskayuna NY
John Thomas Pedicone - Orlando FL
Assignee:
General Electric Company - Schenectady NY
International Classification:
D02G 300
US Classification:
428398
Abstract:
The present invention discloses an acoustic composite material for an ultrasonic phased array and a method for making. The acoustic composite material is formed from a microcapillary array having a plurality of holes of a constant cross-section and volume fraction. In each of the plurality of holes of the microcapillary array, a polymer fill is deposited therein. The polymer filled microcapillary array is cut at an axis perpendicular to the microcapillary array into a plurality of sections. Each of the plurality of sections are then ground into a predetermined thickness and bonded to a phased array of piezoelectric elements and backfill material.

Method And Apparatus For Digital Phased Array Imaging

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US Patent:
49839705, Jan 8, 1991
Filed:
Mar 28, 1990
Appl. No.:
7/500164
Inventors:
Matthew O'Donnell - Schenectady NY
William E. Engeler - Scotia NY
John J. Bloomer - Schenectady NY
John T. Pedicone - Schenectady NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H03M 154
US Classification:
341122
Abstract:
A method for generating a stream of digital data words, each representing an analog signal amplitude from a beam of vibratory energy received by a plurality N of transducers each associated with one of a like number of separate channels of a phased array, uses the steps of: sampling, after a delay of a multiple number of cycles at a fixed frequency F, an analog input signal in each channel at a fixed frequency F for conversion to a digital data word at each sample; then demodulating the digital data word stream in each channel to baseband and reducing the data word rate by a factor D; and phase-rotating the baseband data stream of each channel by a phase difference. DELTA. phi. determined by the focal range R and steering angle. theta. to obtain, along both the sampling delay, a different channel time delay t. sub. d,j, for each j-th channel, where 1. ltoreq. j. ltoreq.

Static Cmos Programmable Logic Array

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US Patent:
47822490, Nov 1, 1988
Filed:
Aug 3, 1987
Appl. No.:
7/081076
Inventors:
William E. Engeler - Scotia NY
Menahem Lowy - Schenectady NY
John T. Pedicone - Schenectady NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H03K 19177
US Classification:
307469
Abstract:
A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.

Method Of Making An Acoustic Composite Material For An Ultrasonic Phased Array

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US Patent:
55520049, Sep 3, 1996
Filed:
Apr 3, 1995
Appl. No.:
8/415903
Inventors:
Peter W. Lorraine - Niskayuna NY
John T. Pedicone - Orlando FL
International Classification:
H01L 4108
G01N 2900
H04R 1700
US Classification:
156154
Abstract:
The present invention discloses an acoustic composite material for an ultrasonic phased array and a method for making. The acoustic composite material is formed from a microcapillary array having a plurality of holes of a constant cross-section and volume fraction. In each of the plurality of holes of the microcapillary array, a polymer fill is deposited therein. The polymer filled microcapillary array is cut at an axis perpendicular to the microcapillary array into a plurality of sections. Each of the plurality of sections are then ground into a predetermined thickness and bonded to a phased array of piezoelectric elements and backfill material.

Apparatus For Implementation Of Desired Input/Output Function In An Electronic System Having A Plurality Of Channels

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US Patent:
50477714, Sep 10, 1991
Filed:
May 3, 1990
Appl. No.:
7/518600
Inventors:
William E. Engeler - Scotia NY
Matthew O'Donnell - Schenectady NY
John J. Bloomer - Schenectady NY
John T. Pedicone - Schenectady NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H03M 112
US Classification:
341140
Abstract:
Apparatus for providing a desired output signal as a function of a single-valued input signal in an electronic system, includes: an addressable memory, having a plurality L locations, each for storage of a data word of B bits; a circuit for storing in each of the L locations of the memory means a B-bit data word having a value selected to provide a particular output value; and circuitry for converting a present single-valued increment of input signal to a unique address, within the range of allowable locations of the memory, to cause each increment of input signal to select the associated one of the L data word locations, from which to output corresponding data.

Utrasound Imaging System Architecture Employing Switched Transducer Elements

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US Patent:
58329234, Nov 10, 1998
Filed:
Dec 11, 1996
Appl. No.:
8/763772
Inventors:
William Ernest Engeler - Scotia NY
Peter William Lorraine - Niskayuna NY
John Thomas Pedicone - Winter Springs FL
Assignee:
General Electric Company - Schenectady NY
International Classification:
A61B 800
US Classification:
12866101
Abstract:
An ultrasonic imaging system which uses transform beamforming in a two-dimensional context includes a two-dimensional array of transducer elements, a plurality of groups of local busses, and a plurality of sets of switching circuits. Each transducer element has a signal electrode coupled to a corresponding set of switching circuits which is controlled so that a particular transducer element is selectively coupled to one of the associated group of local busses. Each local bus provides an output signal that is sent from the probe to the console via a respective coaxial cable for each group of local busses. The number of connections that are necessary to be made through each coaxial cable is reduced by the ratio of the number of transducer elements coupled to a set of local busses and the number of busses in that set. Each set of local busses provides the input transform signals to one transform section of the transform preprocessor. A control signal stored in memory determines which local bus each transducer is operatively connected to.
John T Pedicone from New Smyrna Beach, FL, age ~67 Get Report