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Joao M Geada

from Chelmsford, MA
Age ~59
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Also known as:
Joan Geada
Phone and address:
66 Mill Rd, Kates Corner, MA 01824
(978) 502-0825
Related to:
Isabelle Geada, 24
Connected to:
Juan R Geada, 73Sandra Geada, 49Levi O Geadelmann, 44Jeremy M Geagan, 50Marguerite Geagan, 60Sarah Geagea, 28Mirela Geagla, 62Michael J Geagley, 50Paul D Geaglone, 40Priscilla C Geahigan, 83

Joao Geada Phones & Addresses

  • 66 Mill Rd, Chelmsford, MA 01824 (978) 502-0825
  • 70 Boston Rd, Chelmsford, MA 01824
  • Peekskill, NY
  • 66 Mill Rd, Chelmsford, MA 01824

Resumes

Resumes

Joao Geada Photo 1

Chief Technologist

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Location:
Chelmsford, MA
Industry:
Computer Software
Work:
CLK Design Automation since Dec 2004
Chief Technology Officer
Education:
University of Newcastle upon Tyne 1987 - 1991
University of Newcastle upon Tyne 1983 - 1987
Skills:
Verilog
Eda
C++
Simulations
Asic
Debugging
Distributed Systems
Soc
Tcl
Static Timing Analysis
Statistical Timing Analysis
Multithreading
Algorithms
Systemverilog
Semiconductors
System on A Chip
Fluent English
Fluent Spanish
Fluent Portuguese
Compilers
Parallel Computing
Innovation
Parallel Algorithms
Machine Learning
Big Data Analytics
Joao Geada Photo 2

Joao Geada

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Position:
Chief Technology Officer at CLK Design Automation
Location:
Greater Boston Area
Industry:
Computer Software
Work:
CLK Design Automation since Dec 2004
Chief Technology Officer
Education:
University of Newcastle upon Tyne 1987 - 1991
University of Newcastle upon Tyne 1983 - 1987
Skills:
Fluent English
Fluent Spanish
Fluent Portuguese
Verilog
EDA
Static Timing Analysis
Statistical Timing Analysis
Compilers
Distributed Systems
Parallel Computing
Multithreading
Innovation
Parallel Algorithms

Business Records

Name / Title
Company / Classification
Phones & Addresses
Joao Geada
Chief Architect
CLK Design Automation
Computer Software · Management Consulting Services · Other Technical Consulting Svcs
305 Foster St SUITE 203, Littleton, MA 01460
295 Foster St, Littleton, MA 01460
(978) 486-1056

Publications

Us Patents

Multi-Engine Static Analysis

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US Patent:
7793243, Sep 7, 2010
Filed:
Dec 4, 2006
Appl. No.:
11/566543
Inventors:
Murat R. Becer - Cedar Park TX, US
Joao M. Geada - Chelmsford MA, US
Lee La France - Bolton MA, US
Nicholas Rethman - North Andover MA, US
Qian Shen - Shrewsbury MA, US
Assignee:
CLK Design Automation, Inc. - Littleton MA
International Classification:
G06F 17/50
G06F 17/30
US Classification:
716 6, 716 1, 716 4, 716 5, 716 7, 707 10
Abstract:
A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.

Database Based Timing Variation Analysis

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US Patent:
20130227510, Aug 29, 2013
Filed:
Feb 28, 2012
Appl. No.:
13/407241
Inventors:
Isadore T. Katz - Harvard MA, US
Joao M. Geada - Chelmsford MA, US
Leon LaFrance - Bolton MA, US
Ferenc Varadi - Worcester MA, US
Ahran Dunsmoor - Pepperell MA, US
James Kuzeja - Pepperell MA, US
Shiva Raja - Chelmsford MA, US
Assignee:
CIk Design Automation, Inc. - Littleton MA
International Classification:
G06F 17/50
US Classification:
716113
Abstract:
A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.

Timing Variation Characterization

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US Patent:
7594210, Sep 22, 2009
Filed:
Nov 16, 2006
Appl. No.:
11/560553
Inventors:
Murat R. Becer - Cedar Park TX, US
Joao M. Geada - Chelmsford MA, US
Isadore T. Katz - Harvard MA, US
Lee La France - Bolton MA, US
Assignee:
CLK Design Automation, Inc. - Littleton MA
International Classification:
G06F 17/50
US Classification:
716 6, 716 7, 703 16
Abstract:
A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells; and computing data characterizing a relationship between a variability of delay and a magnitude of delay shared among the cells in the family of cells.
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Joao M Geada from Chelmsford, MA, age ~59 Get Report