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Jinhong H Tong

from Santa Clara, CA
Age ~51
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Also known as:
Jin H Tong, Hong Tong Jinhong, Enrique Welcher, Jing Wang
Phone and address:
3003 Mauricia Ave, Santa Clara, CA 95051
(408) 246-5469
Related to:
Wei Richard Wang, 59Yue Wang, 36Yali Wang, 44Wang Gang
Connected to:
Adams N Tong, 50Agnes K Tong, 52Amy K Tong, 52Angelina D Tong, 28Anne M Tong, 55Arthur D Tong, 79Bethany J Tong, 41Carol A Tong, 63Chai K Tong, 56Chee L Tong, 48

Jinhong Tong Phones & Addresses

  • 3003 Mauricia Ave, Santa Clara, CA 95051 (408) 246-5469
  • 1901 Halford Ave, Santa Clara, CA 95051
  • West Covina, CA
  • 1712 Hickory St, Denton, TX 76201 (940) 383-8716
  • Plano, TX
  • San Jose, CA

Work

Company: Hgst, a western digital company Apr 2012 Address: San Jose, CA Position: Principal process integration engineer

Education

Degree: Ph.D School / High School: University of North Texas 1999 to 2003 Specialities: Chemistry

Skills

Thin Films • Cvd • Characterization • Semiconductors • Semiconductor Industry • Afm • Sputtering • Jmp • Powder X Ray Diffraction • Xps • Design of Experiments • Materials • Process Integration • Atomic Layer Deposition • Ellipsometry • Ald • Pvd • Etching • R • Physical Vapor Deposition • Chemical Vapor Deposition

Languages

English

Industries

Semiconductors

Resumes

Resumes

Jinhong Tong Photo 1

Principal Process Integration Engineer

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Location:
3003 Mauricia Ave, Santa Clara, CA 95051
Industry:
Semiconductors
Work:
HGST, a Western Digital company - San Jose, CA since Apr 2012
Principal Process Integration Engineer
Intermolecular Sep 2005 - May 2012
Sr. Process Engineer
Education:
University of North Texas 1999 - 2003
Ph.D, Chemistry Beijing University of Chemical Technology 1996 - 1999
MS, Analytical Chemistry Beijing University of Chemical Technology 1991 - 1995
BS, Analytical Chemistry
Skills:
Thin Films
Cvd
Characterization
Semiconductors
Semiconductor Industry
Afm
Sputtering
Jmp
Powder X Ray Diffraction
Xps
Design of Experiments
Materials
Process Integration
Atomic Layer Deposition
Ellipsometry
Ald
Pvd
Etching
R
Physical Vapor Deposition
Chemical Vapor Deposition
Languages:
English

Publications

Us Patents

Methods For Forming Resistive Switching Memory Elements

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US Patent:
7678607, Mar 16, 2010
Filed:
Feb 5, 2007
Appl. No.:
11/702725
Inventors:
Tony Chiang - Campbell CA, US
Chi-I Lang - Sunnyvale CA, US
Jinhong Tong - Santa Clara CA, US
Nitin Kumar - Menlo Park CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438104, 438171, 438678, 257 4, 365148
Abstract:
Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Methods For Forming Resistive Switching Memory Elements

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US Patent:
7704789, Apr 27, 2010
Filed:
Feb 5, 2007
Appl. No.:
11/702967
Inventors:
Nitin Kumar - Menlo Park CA, US
Jinhong Tong - Santa Clara CA, US
Chi-I Lang - Sunnyvale CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438104, 438171, 438678, 257 4
Abstract:
Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Substrate Processing Including A Masking Layer

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US Patent:
7879710, Feb 1, 2011
Filed:
Dec 29, 2006
Appl. No.:
11/647882
Inventors:
Zachary Fresco - San Jose CA, US
Chi-I Lang - San Jose CA, US
Sandra G. Malhotra - San Jose CA, US
Tony P. Chiang - San Jose CA, US
Thomas R. Boussie - Menlo Park CA, US
Nitin Kumar - San Jose CA, US
Jinhong Tong - San Jose CA, US
Anh Duong - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
438597, 438622, 438624, 438761, 438763, 257E2126, 257E21265
Abstract:
Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Methods For Treating Substrates In Preparation For Subsequent Processes

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US Patent:
7884036, Feb 8, 2011
Filed:
Jul 12, 2007
Appl. No.:
11/777152
Inventors:
Jinhong Tong - Santa Clara CA, US
Anh Duong - Union City CA, US
Chi-I Lang - Cupertino CA, US
Sandra Malhotra - San Jose CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438798, 438597, 438758, 438795, 257E21001
Abstract:
Methods for treating a substrate in preparation for a subsequent process are presented, the method including: receiving the substrate, the substrate comprising conductive regions and dielectric regions; and applying an oxidizing agent to the substrate in a manner so that the dielectric regions are oxidized to become increasingly hydrophilic to enable access to the conductive regions in the subsequent process, wherein the dielectric region is treated to a depth in the range of approximately 1 to 5 atomic layers. In some embodiments, methods further include processing the substrate, wherein processing the conductive regions are selectively enhanced. In some embodiments, the oxidizing agent includes atmospheric pressure plasma and UV radiation.

Methods For Forming Resistive Switching Memory Elements

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US Patent:
7972897, Jul 5, 2011
Filed:
Feb 5, 2007
Appl. No.:
11/702966
Inventors:
Nitin Kumar - Menlo Park CA, US
Chi-I Lang - Sunnyvale CA, US
Tony Chiang - Campbell CA, US
Jinhong Tong - Santa Clara CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/00
US Classification:
438104, 438171, 438678
Abstract:
Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Nonvolatile Memory Elements With Metal-Deficient Resistive-Switching Metal Oxides

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US Patent:
8097878, Jan 17, 2012
Filed:
Mar 5, 2007
Appl. No.:
11/714326
Inventors:
Nitin Kumar - Menlo Park CA, US
Jinhong Tong - Santa Clara CA, US
Chi-I Lang - Sunnyvale CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 29/12
H01L 29/02
US Classification:
257 43, 257 2, 257 4, 257E29002, 257E29068
Abstract:
Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Formation Of A Zinc Passivation Layer On Titanium Or Titanium Alloys Used In Semiconductor Processing

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US Patent:
8143164, Mar 27, 2012
Filed:
Feb 9, 2009
Appl. No.:
12/368110
Inventors:
Bob Kong - Newark CA, US
Chi-I Lang - Sunnyvale CA, US
Jinhong Tong - San Jose CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438689, 438678, 438694, 438745, 438613, 428620, 510175
Abstract:
Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl, and a pH adjuster.

Methods For Forming Nickel Oxide Films For Use With Resistive Switching Memory Devices

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US Patent:
8283214, Oct 9, 2012
Filed:
Dec 21, 2007
Appl. No.:
11/963656
Inventors:
Jinhong Tong - Santa Clara CA, US
Chi-I Lang - Sunnyvale CA, US
Tony Chiang - Campbell CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/20
H01L 21/00
H01L 21/16
H01L 21/8229
US Classification:
438141, 438104, 257E21613
Abstract:
Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)film on the substrate, where the forming the Ni(OH)occurs at the cathode; and annealing the Ni(OH)film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, an Ru alloy, and an Rh alloy.
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Jinhong H Tong from Santa Clara, CA, age ~51 Get Report