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Jia J Chen

from College Point, NY
Age ~50

Jia Chen Phones & Addresses

  • 6485 Saunders St APT A5, Rego Park, NY 11374
  • College Point, NY
  • Verona, NJ
  • Millburn, NJ
  • Auburndale, MA
  • Toledo, OH
  • Bayport, NY
  • Dededo, GU

Professional Records

Lawyers & Attorneys

Jia Chen Photo 1

Jia Chen, New York NY - Lawyer

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Address:
Law Office of Xiumin Chen, PLLC
7 Chatham Sq Rm 201, New York, NY 10038
(212) 566-6998 (Office)
Licenses:
New York - Currently registered 2011
Education:
University of Iowa College of Law
Jia Chen Photo 2

Jia Chen - Lawyer

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Address:
China Investment Corporation Legal & Compliance Deptment
(108) 409-6235 (Office)
Licenses:
New York - Currently registered 2001
Education:
New York University School of Law
Jia Chen Photo 3

Jia Chen - Lawyer

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Licenses:
New York - Currently registered 2008
Education:
University of Minnesota Law School
Jia Chen Photo 4

Jia Chen - Lawyer

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Office:
Morgan, Lewis & Bockius LLP
ISLN:
919700732
Admitted:
2008
University:
University of California, Berkeley, B.S., 2002
Law School:
University of Minnesota Law School, J.D., 2007

Public records

Vehicle Records

Jia Chen

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Address:
536 115 St APT A, College Point, NY 11356
Phone:
(347) 732-0391
VIN:
3VWLZ7AJ1BM368249
Make:
VOLKSWAGEN
Model:
JETTA
Year:
2011

Jia Chen

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Address:
6919 226 St, Oakland Gardens, NY 11364
Phone:
(646) 209-6828
VIN:
JTJBC1BA8A2026702
Make:
LEXUS
Model:
RX 450H
Year:
2010

Resumes

Resumes

Jia Chen Photo 5

Jia Le Chen Brooklyn, NY

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Work:
Mini-Circuits

Sep 2012 to 2000
Purchasing Agent

Mini-Circuits
Brooklyn, NY
Sep 2012 to Oct 2012
Purchasing Assistant

Wirtz Manufacturing Co. Inc
Port Huron, MI
Oct 2010 to Aug 2012
Project Manager

Wirtz Mfg. Co. Inc. (Changzhou)
Changzhou, China
Oct 2011 to Jul 2012
Plant General Manager

Allied Technology, Inc
Romulus, MI
May 2010 to Oct 2010
Procurement Specialist

Education:
Michigan State University, Eli Broad College of Business
East Lansing, MI
2006 to 2010
Bachelor of Arts in Supply Chain Management

Skills:
Supply Chain Management, Inventory Management, Operation Management, Procurement, Total Quality Management, ERP, Electronic Component, Blueprint, LEAN, Project Management, Supplier Management and Selection, Global Sourcing
Jia Chen Photo 6

Jia Chen Chen Oakland Gardens, NY

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Work:
A Dan America Inc

Jun 2011 to Present
Marketing manager

49 Maspeth Avenue LLC
Brooklyn, NY
Jan 2010 to May 2011
Experienced Real Estate Assistant

Hofstra University
Hempstead, NY
Dec 2009 to May 2011
Responsible Library Assistant

Wokmania Restaurant

Feb 2008 to Mar 2009
Cashier & Customer Service

SuZhou Victory Precision Manufacture CO, .LTD
Suzhou, CN
Jan 2006 to Sep 2006
Technician

Education:
Frank G. Zar School of Business, Hofstra University
Hempstead, NY
May 2011
M.B.A. in Marketing

University of Sheffield
Sheffield
Nov 2008
M.S. in Material Engineering

Sheffield Internation college
Sheffield
May 2007
Graduate Diploma in Science and Engineering

Nanjing University of Technology
Nanjing, CN
Jun 2006
B.S. in Material Engineering

Skills:
Quickbooks. Microsoft (Word, Excel, Access, PowerPoint, outlook), Minitab. Fluent in Mandarin and English . Own NY State Drivers License and personal vehicle
Jia Chen Photo 7

Jia Wei Chen Quincy, MA

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Work:
Young-Cheul Kim Research Lab

Sep 2011 to 2000
Independent Study Student

Young-Cheul Kim Research Lab

Sep 2011 to 2000
Work Study Research Assistant

Jeanne Hardy Research Group

Sep 2010 to May 2011
Work Study Lab Assistant

Northeastern University

Jun 2010 to Aug 2010
Summer Internship Student

Quincy Medical Center
Quincy, MA
May 2008 to Aug 2008
Volunteer

Education:
University of Massachusetts Amherst, School of Natural Science
Amherst, MA
May 2012
Bachelor of Science in Biochemistry and Microbiology

Jia Chen Photo 8

Jia Chen Copiague, NY

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Work:
sun wah

Jan 2009 to Present
cashier

Carvel
Copiague, NY
Jun 2009 to Jan 2010
Crew member

Education:
Nassau community college
Garden City, NY
Jan 2010 to Jan 2014
Accounting

Skills:
Microsoft Works proficient, internet proficient, and proficient cashier
Jia Chen Photo 9

Jia Chen New York, NY

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Work:
Sing Tao Daily
New York, NY
Feb 2012 to Jun 2012
Editorial Office of Sing Tao Daily

Pancare Pharmacy
New York, NY
Oct 2011 to Feb 2012
Receptionist of Pancare Pharmacy

the Law Office of Gregory Kuntashian
New York, NY
Sep 2011 to Oct 2011
Clerk of Gregory Kuntashian

Education:
Xiamen University
Xiamen, CN
Sep 2007 to Jun 2011
Bachelor of Arts in English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ms. Jia Jie Chen
Owner
Jia Jie Chen
Professional Services (General)
7401 E. Brainerd Road, Suite 100, Chattanooga, TN 37421
Jia Chen
Chairman
Phoenix Real Estate Investment
Real Estate Agents and Managers
88 Forest Avenue, Matinecock, NY 11560
Jia Chen
Director
WE-CONTACT, INC
28 Thoreau St, North Billerica, MA 01862
25 Clark St, Dedham, MA 02026
Jia Chen
Principal
Hung Hing Chinese Restaur
Eating Place
239 Bedford Park Blvd, Bronx, NY 10458
Jia Q. Chen
Medical Doctor
Surgical Associates
Medical Doctor's Office
530 1 Ave, New York, NY 10016
(212) 263-7302
Jia Chen
Chairman
Phoenix Real Estate Investment
88 Frst Ave, Locust Valley, NY 11560
(408) 200-1900
Jia Bin Chen
J B WORKS, LLC
49 High Rdg Rd, Stamford, CT 06905
74 E Rdg Rd, Stamford, CT 06903
Jia L. Chen
Simple Solution Enterprise LLC
Business Services
6410 Bay Pkwy, Brooklyn, NY 11204
Jia Chen
Chairman
Phoenix Real Estate Investment
Real Estate Agents and Managers
88 Forest Avenue, Matinecock, NY 11560

Publications

Us Patents

Split Poly-Sige/Poly-Si Alloy Gate Stack

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US Patent:
6927454, Aug 9, 2005
Filed:
Oct 7, 2003
Appl. No.:
10/680820
Inventors:
Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L029/76
US Classification:
257336, 257 19, 257 20, 257 24, 257192, 257213, 257344, 257392
Abstract:
A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Solid Phase Sensors

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US Patent:
7008547, Mar 7, 2006
Filed:
Mar 7, 2003
Appl. No.:
10/383380
Inventors:
Jia Ming Chen - Plainsboro NJ, US
Yongchi Tian - Princeton NJ, US
Zilan Shen - West Windsor NJ, US
Pradyumna Swain - Franklin Park NJ, US
Assignee:
Sarnoff Corporation - Princeton NJ
International Classification:
B44C 1/22
H01B 13/00
H01L 21/461
G01N 15/06
G01N 27/00
US Classification:
216 11, 216 13, 216 16, 216 41, 216 56, 216 58, 216 72, 216 74, 422 50, 422 681, 422 8201, 422 83, 422 98, 436 43, 436149, 436151, 73 101, 73 102, 438 21, 438400, 438689, 438735, 29592, 295921
Abstract:
Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a single substrate.

Split Poly-Sige/Poly-Si Alloy Gate Stack

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US Patent:
7378336, May 27, 2008
Filed:
May 9, 2005
Appl. No.:
11/124978
Inventors:
Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/3205
US Classification:
438592, 438593, 257413
Abstract:
A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Reduction Of Silicide Formation Temperature On Sige Containing Substrates

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US Patent:
7384868, Jun 10, 2008
Filed:
Sep 15, 2003
Appl. No.:
10/662900
Inventors:
Cyril Cabral, Jr. - Ossining NY, US
Roy A. Carruthers - Stormville NY, US
Jia Chen - Ossining NY, US
Christophe Detavernier - Ossining NY, US
James M. Harper - Durham NH, US
Christian Lavoie - Ossining NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438682, 438597, 438683
Abstract:
A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

Method Of Forming A Split Poly-Sige/Poly-Si Alloy Gate Stack

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US Patent:
7465649, Dec 16, 2008
Filed:
Aug 30, 2007
Appl. No.:
11/847384
Inventors:
Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/3205
US Classification:
438592, 438593, 257413
Abstract:
A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Complementary Carbon Nanotube Triple Gate Technology

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US Patent:
7492015, Feb 17, 2009
Filed:
Nov 10, 2005
Appl. No.:
11/164109
Inventors:
Jia Chen - Ossining NY, US
Edward J. Nowak - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/092
US Classification:
257369, 257 40, 257E51006, 257E5104, 977742, 977940
Abstract:
Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.

Split Poly-Sige/Poly-Si Alloy Gate Stack

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US Patent:
7666775, Feb 23, 2010
Filed:
Apr 17, 2008
Appl. No.:
12/104570
Inventors:
Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US
Assignee:
International Businesss Machines Corporation - Armonk NY
International Classification:
H01L 21/3205
US Classification:
438592, 438593, 257413
Abstract:
A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Carbon Nanotube Diodes And Electrostatic Discharge Circuits And Methods

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US Patent:
7872334, Jan 18, 2011
Filed:
May 4, 2007
Appl. No.:
11/744234
Inventors:
Jia Chen - Ossining NY, US
Steven Howard Voldman - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 51/30
US Classification:
257653, 257E5104, 977750
Abstract:
Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.
Jia J Chen from College Point, NY, age ~50 Get Report