Jerome Jean Ribo

7376528, May 20, 2008

Apr 13, 2004

10/822806

Jerome J. Ribo - San Jose CA, US

Kawasaki LSI U.S.A., Inc. - San Jose CA

G01D 3/00

702108

When used as a test data generator, CDR internal structures may be applied to generate drift conditions in the test data. For example, a finite state machine phase shifts a clock signal, over time, driving the test data generator thereby producing a drift condition on the test data. Once the test is completed, one of the other CDRs may be used as a tester to similarly generate test data for the first CDR. CDRs may be configured in pairs for this purpose so that one may be used to test the other.

8396180, Mar 12, 2013

Dec 18, 2008

12/314897

Jerome J. Ribo - San Jose CA, US

Kawasaki Microelectronics America Inc. - San Jose

H04L 7/00
H04B 7/02
H04W 4/00

375371, 370338, 375267

Aspects of the disclosure provide a method and an apparatus for clock and data recovery. The method and apparatus can increase jitter tolerance, and can provide recovered data with reduced jitter amplitude. The method for recovering data transmitted over a channel can include detecting a phase of a data transition within a full unit interval that includes an active zone and an inactive zone that are set based on a jitter characteristic for the channel, generating a phase directive when the phase of the data transition is located within the active zone, and adjusting a data sampling phase based on the phase directive, so that the data transmitted over the channel is sampled at a data transition edge free location.

20050238126, Oct 27, 2005

Apr 21, 2004

10/828318

Jerome Ribo - San Jose CA, US
Benoit Roederer - Cupertino CA, US

KAWASAKI LSI U.S.A., INC. - San Jose CA

H04L007/00

375355000, 375326000

A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the phase shifted clocks and define N sampling points where a serial data stream is sampled. The multi-phase oversampling technique provides at least two sampling points per data bit of the serial data stream at highest data rates. The sampling points divide one clock cycle of the single clock into N zones. Depending on which of the zones a data edge transition is detected, the CDR can converge the sampling points to optimal data sampling positions in the serial data stream.