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Jean-Michel Caia Phones & Addresses

  • 5301 Old Sacramento Rd, Plymouth, CA 95669 (209) 245-6055

Publications

Us Patents

Transport Network System With Transparent Transport And Method Of Operation Thereof

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US Patent:
8392788, Mar 5, 2013
Filed:
Nov 24, 2009
Appl. No.:
12/625551
Inventors:
Juan-Carlos Calderon - Fremont CA, US
Arun Zarabi - Sacramento CA, US
Jean-Michel Caia - Plymouth CA, US
Assignee:
Cortina Systems, Inc. - Sunnyvale CA
International Classification:
H03M 13/00
US Classification:
714752, 714755
Abstract:
A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy.

Signal Format Conversion Apparatus And Methods

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US Patent:
8494363, Jul 23, 2013
Filed:
Apr 21, 2011
Appl. No.:
13/091908
Inventors:
Juan-Carlos Calderon - Fremont CA, US
Jean-Michel Caia - Plymouth CA, US
Arun Zarabi - Sacramento CA, US
Aws Shallal - Cary NC, US
Theron Paul Niederer - Raleigh NC, US
Assignee:
Cortina Systems, Inc. - Sunnyvale CA
International Classification:
H04B 10/00
US Classification:
398 43, 398154, 370503, 370506
Abstract:
Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.

Techniques To Buffer Traffic In A Communications System

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US Patent:
20070086479, Apr 19, 2007
Filed:
Feb 21, 2006
Appl. No.:
11/359819
Inventors:
Jing Ling - Fremont CA, US
Jean-Michel Caia - Plymouth CA, US
Alejandro Beracoechea - Phoenix AZ, US
International Classification:
H04L 12/66
US Classification:
370463000
Abstract:
Techniques are described herein that may be used to buffer traffic received at a communications device. For example, a buffer external from a traffic processor may be used to buffer traffic in ingress or egress directions. For example, a bandwidth in each of directions of to and from the buffer may be less than a sum of maximum bandwidths in ingress and egress directions. For example, a single memory interface may be used to communicatively couple the buffer and the traffic processor.

System And Method For Accounting For Time That A Packet Spends In Transit Through A Transparent Clock

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US Patent:
20130100832, Apr 25, 2013
Filed:
Oct 21, 2011
Appl. No.:
13/279043
Inventors:
Jasson Flinn - Ottawa, CA
Juan-Carlos Calderon - Fremont CA, US
Jean-Michel Caia - Plymouth CA, US
Arun Zarabi - Sacramento CA, US
Scott Feller - Mountain View CA, US
Assignee:
CORTINA SYSTEMS, INC. - Sunnyvale CA
International Classification:
H04L 12/26
US Classification:
370252
Abstract:
Despite a recent revision, IEEE 1588™-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.

Apparatus And Method For Forward Error Correction Over A Communication Channel

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US Patent:
20160344512, Nov 24, 2016
Filed:
Aug 5, 2016
Appl. No.:
15/230319
Inventors:
- Santa Clara CA, US
Jean-Michel Caia - Plymouth CA, US
Arash Farhoodfar - Sunnyvale CA, US
Arun Zarabi - Sacramento CA, US
International Classification:
H04L 1/00
H04B 10/516
H04B 10/27
H04J 14/02
Abstract:
There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).

Apparatus And Method For Communicating Data Over A Communication Channel

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US Patent:
20150003827, Jan 1, 2015
Filed:
Jun 3, 2014
Appl. No.:
14/295054
Inventors:
- Sunnyvale CA, US
Jean-Michel Caia - Plymouth CA, US
Arash Farhoodfar - Sunnyvale CA, US
Arun Zarabi - Sacramento CA, US
Michael Miller - Raleigh NC, US
Assignee:
CORTINA SYSTEMS, INC. - Sunnyvale CA
International Classification:
H04B 10/27
H04J 3/16
US Classification:
398 43
Abstract:
Provided is an apparatus and method for transmitting data over a communication channel having at least one physical lane for transmitting data. The apparatus includes, for each physical lane, allocation circuitry configured for allocating data in logical lanes corresponding to the physical lane. The apparatus also includes, for each physical lane, a multiplexer configured for bit-interleaving the data from the logical lanes corresponding to the physical lane into interleaved data for transmission over the physical lane. In accordance with an embodiment of the present disclosure, for each physical lane, the allocation circuitry is configured for allocating the data such that the interleaved data for transmission over the physical lane has clusters of sequential bits of the same symbol. Thus, upon transmission and reception by a receiver, any correlated errors affecting sequential bits may affect fewer symbols. Also provided is an apparatus and method for receiving data in a complementary manner.

Apparatus And Method For Forward Error Correction Over A Communication Channel

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US Patent:
20140270780, Sep 18, 2014
Filed:
Mar 14, 2014
Appl. No.:
14/211938
Inventors:
- Sunnyvale CA, US
Jean-Michel Caia - Plymouth CA, US
Arash Farhoodfar - Sunnyvale CA, US
Arun Zarabi - Sacramento CA, US
Assignee:
CORTINA SYSTEMS, INC. - Sunnyvale CA
International Classification:
H04L 1/00
H04B 10/516
H04J 14/02
US Classification:
398 79, 398193
Abstract:
There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).

Reducing Delay And Delay Variation In A Buffer In Network Communications

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US Patent:
20140164546, Jun 12, 2014
Filed:
Oct 18, 2011
Appl. No.:
13/276308
Inventors:
Dennis Albert DOIDGE - Apex NC, US
Juan-Carlos CALDERON - Fremont CA, US
Jean-Michel CAIA - Plymouth CA, US
Assignee:
CORTINA SYSTEMS, INC. - Sunnyvale CA
International Classification:
G06F 15/167
US Classification:
709213
Abstract:
There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.
Jean-Michel Caia from Plymouth, CA Get Report