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Jang Sup Yoon

from Santa Clara, CA
Age ~57
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Also known as:
Jang S Yoon, Jangsup Yoon, Jangsup Sup Yoon, Sup Yoon Jang
Related to:
Dennis Jia Ju, 42Jangsup Yoon, 68Christine K Yoon, 42Changwoo Yoon, 57Insook Yoon, 52Wonsub Y Oon, 56Sung H Yoon, 60Young Sim YoonkimKim Young Sim Yoon, 57Sung R Yoon, 33
Connected to:
Alan H Yoon, 29Albert T Yoon, 50Alexis S Yoon, 57Angie M Yoon, 63Bryan E Yoon, 58Carrie J Yoon, 53Christell A Yoon, 77Clara S Yoon, 54Danielle Yoon, 30Darmie K Yoon, 63

Jang Yoon Phones & Addresses

  • Santa Clara, CA
  • Mountain View, CA
  • Queen Creek, AZ
  • Camarillo, CA
  • Gainesville, FL
  • Thousand Oaks, CA
  • Scottsdale, AZ
  • Maricopa, AZ

Professional Records

Medicine Doctors

Jang Yoon Photo 1

Jang Won Yoon

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Publications

Us Patents

Embedded Ic Test Circuits And Methods

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US Patent:
7379716, May 27, 2008
Filed:
Mar 24, 2005
Appl. No.:
11/088933
Inventors:
William R. Eisenstadt - Gainesville FL, US
Robert M. Fox - Gainesville FL, US
Jang Sup Yoon - Gainesville FL, US
Tao Zhang - Gainesville FL, US
Assignee:
University of Florida Research Foundation, Inc. - Gainesville FL
International Classification:
H04B 1/04
US Classification:
455126, 4551272, 4551151
Abstract:
A self-testing transceiver having an on-chip power detection capability is provided. The self-testing transceiver can include a semiconductor substrate and a transmitter having a high-power amplifier disposed on the substrate. The self-testing transceiver also can include a receiver disposed on the substrate for selectively coupling to an antenna. The self-testing transceiver can further include at least one power detector disposed on the semiconductor substrate for determining a power such as an RMS and/or peak-power of a signal at an internal node of the self-testing transceiver. Additionally, the self-testing transceiver can include a loopback circuit disposed on the substrate.

System, Device, And Method For Embedded S-Parameter Measurement

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US Patent:
7924025, Apr 12, 2011
Filed:
Jul 25, 2006
Appl. No.:
11/996913
Inventors:
William R. Eisenstadt - Gainesville FL, US
Robert M. Fox - Gainesville FL, US
Jang Sup Yoon - Gainesville FL, US
Assignee:
University of Florida Research Foundation, Inc. - Gainesville FL
International Classification:
G01R 27/02
G01R 27/32
US Classification:
324638, 324601, 702 85
Abstract:
An embedded s-parameter measurement system for measuring or determining an s-parameter is provided. The system includes an s-parameter test circuit for connecting to a port of a high-frequency multi-port device-under-test (DUT). The s-parameter test circuit includes a directional coupler for sampling a forward signal conveyed to the DUT and for sampling a reverse signal reflected by the DUT. The s-parameter test circuit also includes a peak detector electrically connected to the directional coupler for detecting a magnitude of a signal conveyed to the peak detector by the directional coupler. The s-parameter test circuit further includes a phase detector electrically connected to the directional coupler for determining a phase of a signal conveyed to the phase detector by the directional coupler, and at least one other s-parameter test circuit for connecting to another port of the high-frequency multi-port DUT.

Power Detector Of Embedded Ic Test Circuits

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US Patent:
7925229, Apr 12, 2011
Filed:
Apr 25, 2008
Appl. No.:
12/109915
Inventors:
William R. Eisenstadt - Gainesville FL, US
Robert M. Fox - Gainesville FL, US
Jang Sup Yoon - Gainesville FL, US
Tao Zhang - Gainesville FL, US
Assignee:
University of Florida Research Foundation, Inc. - Gainesville FL
International Classification:
H04B 1/04
G01R 23/04
US Classification:
4551271, 4551151, 324 95
Abstract:
A self-testing transceiver having an on-chip power detection capability is provided. The self-testing transceiver can include a semiconductor substrate and a transmitter having a high-power amplifier disposed on the substrate. The self-testing transceiver also can include a receiver disposed on the substrate for selectively coupling to an antenna. The self-testing transceiver can further include at least one power detector disposed on the semiconductor substrate for determining a power such as an RMS and/or peak-power of a signal at an internal node of the self-testing transceiver. Additionally, the self-testing transceiver can include a loopback circuit disposed on the substrate.
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Jang Sup Yoon from Santa Clara, CA, age ~57 Get Report