Assignee:
Fujitsu Ltd. - Kanagawa-ken
International Classification:
H03K 1996
Abstract:
A new self clocking family of dynamic logic gates which replace footless or subsequent stage dynamic logic gates in multi-stage domino logic circuits. In a preferred embodiment, a multi-stage logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate and a second stage which includes a new self-clocking dynamic logic gate. The output from the first stage is coupled to the input of the second stage such that the second stage is not dependent upon any type of clock signal for precharging. Instead, the second stage includes a dual transistor arrangement on the inter-stage inputs (i. e. the outputs from one stage which are input to subsequent stages) in order to precharge the output node at the second stage such that no type of clock signal is needed during precharge. Accordingly, the output from the second stage is efficiently precharged without using a delayed clock signal or any customized delay circuitry while minimizing through current by design. This allows the multi-stage domino logic circuit to be designed with lower power consumption since through current is minimized by design.
