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Izak Rosa Bencuya

from Saratoga, CA
Age ~70
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Also known as:
Izak A Bencuya, Izak T Bencuya, Izak B Bencuya, Izak L Bencuya, Izak R Bencuya, Izak Te Bencuya, Isaac Bencuya, Rosa Bencuya, Ari Bencuya, Encoya B Izak
Phone and address:
14793 Vickery Ave, Saratoga, CA 95070
(408) 867-6369
Related to:
Eliot BencuyaRosa GarzaCyndol Wieland, 73Donald L Wieland, 75Pola Bencuya, 93Matthew Wieland, 40
Connected to:
John Bency, 38Gloria J Bencze, 71Jozsef Bencze, 54Steve H Bencze, 68Michelle Benczkowski, 53Altia E Bend, 31Jack Bend, 50Lakenya C Bend, 55Ruth Bend, 54Anna M Benda, 64

Izak Bencuya Phones & Addresses

  • 14793 Vickery Ave, Saratoga, CA 95070 (408) 867-6369 (408) 867-6370 (408) 725-0538
  • Los Angeles, CA
  • 2449 Fayette Dr, New Braunfels, TX 78130
  • Schertz, TX
  • Grain Valley, MO
  • San Jose, CA
  • Viola, IL
  • Guadalupe, TX

Work

Company: Peakwatt solutions Jun 2012 Position: President and chief executive officer

Education

Degree: Master of Business Administration, Masters School / High School: University of California, Berkeley 1994 to 1994 Specialities: Marketing

Skills

Semiconductors • Marketing Strategy • Business Strategy • Operations Management • Semiconductor Device • Executive Management • Executive Pay • Renewable Energy • Energy Efficiency • Energy Management • Semiconductor Industry • Product Development • Product Management • Product Marketing • Product Launch • Strategy • Engineering • Ic • Telecommunications • Characterization • Physics • Analog • Wireless

Languages

English • Hebrew • Turkish

Interests

Collecting Antiques • Exercise • Sweepstakes • Home Improvement • Reading • Gourmet Cooking • Sports • The Arts • Golf • Home Decoration • Cooking • Electronics • Outdoors • Crafts • Music • Family Values • Movies • Collecting • Christianity • Kids • Travel • Boating • Investing • Traveling • International Traavel

Industries

Semiconductors

Resumes

Resumes

Izak Bencuya Photo 1

President And Chief Executive Officer

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Location:
14793 Vickery Ave, Saratoga, CA 95070
Industry:
Semiconductors
Work:
Peakwatt Solutions
President and Chief Executive Officer
Soon
Ok
Education:
University of California, Berkeley 1994 - 1994
Master of Business Administration, Masters, Marketing Yale University 1976 - 1984
Doctorates, Doctor of Philosophy, Applied Science, Engineering, Philosophy Yale University 1978
Master of Science, Masters Boğaziçi University 1972 - 1976
Bachelors, Bachelor of Science, Electrical Engineering Boğaziçi University
Master of Science, Masters University of California, Berkeley, Haas School of Business
Skills:
Semiconductors
Marketing Strategy
Business Strategy
Operations Management
Semiconductor Device
Executive Management
Executive Pay
Renewable Energy
Energy Efficiency
Energy Management
Semiconductor Industry
Product Development
Product Management
Product Marketing
Product Launch
Strategy
Engineering
Ic
Telecommunications
Characterization
Physics
Analog
Wireless
Interests:
Collecting Antiques
Exercise
Sweepstakes
Home Improvement
Reading
Gourmet Cooking
Sports
The Arts
Golf
Home Decoration
Cooking
Electronics
Outdoors
Crafts
Music
Family Values
Movies
Collecting
Christianity
Kids
Travel
Boating
Investing
Traveling
International Traavel
Languages:
English
Hebrew
Turkish

Business Records

Name / Title
Company / Classification
Phones & Addresses
Izak Bencuya
President
BIERA ASSOCIATES, INC
Management Consulting Services · Nonclassifiable Establishments
14793 Vickery Ave, Saratoga, CA 95070
Izak Bencuya
Executive Vice President General Manager And Chief Strategy Officer
Fairchild Semiconductor International, Inc
Mfg Semiconductors & Related Devices
3030 Orch Pkwy, San Jose, CA 95134
82 Running Hl Rd, Portland, ME 04106
(207) 775-8100, (207) 775-8115, (207) 775-8895
Izak Bencuya
Chief Executive Officer
Tabc Turkish American Business Connection
Accounting/Auditing/Bookkeeping
2784 Homestead Rd, Santa Clara, CA 95051

Publications

Us Patents

Low Resistance Package For Semiconductor Devices

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US Patent:
6423623, Jul 23, 2002
Filed:
Aug 27, 1998
Appl. No.:
09/141184
Inventors:
Izak Bencuya - Saratoga CA
Maria Christina B. Estacio - Bacayan, PH
Steven P. Sapp - Felton CA
Consuelo N. Tangpuz - Lapulapu, PH
Gilmore S. Baje - Lapulapu, PH
Rey D. Maligro - Cordova, PH
Assignee:
Fairchild Semiconductor Corporation - Portland ME
International Classification:
H01L 2144
US Classification:
438612, 438613, 438123, 257737, 257738, 257782, 257779, 257780
Abstract:
A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

Field Effect Transistor And Method Of Its Manufacture

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US Patent:
6429481, Aug 6, 2002
Filed:
Nov 14, 1997
Appl. No.:
08/970221
Inventors:
Brian Sze-Ki Mo - Fremont CA
Duc Chau - San Jose CA
Steven Sapp - Felton CA
Izak Bencuya - Saratoga CA
Dean Edward Probst - West Jordan UT
Assignee:
Fairchild Semiconductor Corporation - South Portland MA
International Classification:
H01L 2978
US Classification:
257341, 257331
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Vertical Mosfet With Ultra-Low Resistance And Low Gate Charge

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US Patent:
6696726, Feb 24, 2004
Filed:
Aug 16, 2000
Appl. No.:
09/640955
Inventors:
Izak Bencuya - Saratoga CA
Brian Sze-Ki Mo - Stanford CA
Ashok Challa - West Jordan UT
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 2976
US Classification:
257330, 257331, 257341, 257342
Abstract:
A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.

Field Effect Transistor And Method Of Its Manufacture

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US Patent:
6710406, Mar 23, 2004
Filed:
May 24, 2002
Appl. No.:
10/155554
Inventors:
Brian Sze-Ki Mo - Fremont CA
Duc Chau - San Jose CA
Steven Sapp - Felton CA
Izak Bencuya - Saratoga CA
Dean Edward Probst - West Jordan UT
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 2978
US Classification:
257341, 257331
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method Of Manufacturing A Trench Transistor Having A Heavy Body Region

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US Patent:
6828195, Dec 7, 2004
Filed:
Jan 17, 2003
Appl. No.:
10/347254
Inventors:
Brian Sze-Ki Mo - Fremont CA
Duc Chau - San Jose CA
Steven Sapp - Felton CA
Izak Bencuya - Saratoga CA
Dean Edward Probst - West Jordan UT
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 21336
US Classification:
438270, 438589
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method Of Manufacturing A Trench Transistor Having A Heavy Body Region

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US Patent:
7148111, Dec 12, 2006
Filed:
Aug 27, 2004
Appl. No.:
10/927788
Inventors:
Brian Sze-Ki Mo - Fremont CA, US
Duc Chau - San Jose CA, US
Steven Sapp - Felton CA, US
Izak Bencuya - Saratoga CA, US
Dean E. Probst - West Jordan UT, US
Assignee:
Fairchild Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/336
US Classification:
438270, 438272, 438589
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Field Effect Transistor And Method Of Its Manufacture

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US Patent:
7511339, Mar 31, 2009
Filed:
Jul 30, 2003
Appl. No.:
10/630249
Inventors:
Brian S. Mo - Fremont CA, US
Duc Chau - San Jose CA, US
Steven Sapp - Felton CA, US
Izak Bencuya - Saratoga CA, US
Dean E. Probst - West Jordan UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland MA
International Classification:
H01L 29/78
US Classification:
257341
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method Of Manufacturing A Trench Transistor Having A Heavy Body Region

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US Patent:
7696571, Apr 13, 2010
Filed:
Dec 5, 2008
Appl. No.:
12/329509
Inventors:
Brian Sze-Ki Mo - Fremont CA, US
Duc Chau - San Jose CA, US
Steven Sapp - Felton CA, US
Izak Bencuya - Saratoga CA, US
Dean E. Probst - West Jordan UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 29/78
US Classification:
257341, 257E23086
Abstract:
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
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Izak Rosa Bencuya from Saratoga, CA, age ~70 Get Report