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Irene A Heitsch

from Austin, TX
Age ~63
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Also known as:
Irene Angela Heitsch, Irene A Filaliadib, Irene A Mechtel, Irene A Filali-Adib, Irene B, Irene H
Phone and address:
4413 Destinys Gate Dr, Austin, TX 78727
Related to:
Rose M Molloy, 97Ann Molloy, 70Dennis Molloy, 73Mary LouiseauGrant Louiseau, 42
Connected to:
Cody M Heitschmidt, 49Gerald Heitschmidt, 60Jenna L Heitsch, 37Timothy J Heitsch, 63Travis J Heitsch, 37Karen M Heitshusen, 76Ryan M Heitt, 40Alaina M Heitz, 44Allison N Heitz, 32Andrea K Heitz, 38

Irene Heitsch Phones & Addresses

  • 4413 Destinys Gate Dr, Austin, TX 78727
  • San Marcos, CA
  • 11289 Paseo Montanoso, San Diego, CA 92127
  • Portland, ME
  • 2601 Soldiers Home Rd, West Lafayette, IN 47906
  • W Lafayette, IN
  • W Lafayette, IN

Work

Company: Various Jul 2002 Position: Home educator, community volunteer, student

Education

School / High School: Austin Community College 2013 to 2015 Specialities: Information Science

Skills

Verilog • Functional Verification • Java • Asic • Hardware Architecture • Static Timing Analysis • Microprocessors • Mixed Signal • Electronics • Algorithms • Powerpc • Image Processing • C • Embedded Systems • Teacher Mentoring • Ic • Debugging • Testing • Integrated Circuit Design • Semiconductors • Electrical Engineering • Programming • Peer Mentoring • Mentoring

Ranks

Certificate: License Comp001020642648

Interests

Sustainable Living • Economic Empowerment • Gardening • Nutrition • Education • Technology In Education • Environment • Reading • Hiking • Disaster and Humanitarian Relief

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Irene Heitsch Photo 1

Home Educator, Community Volunteer

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Location:
Austin, TX
Industry:
Electrical/Electronic Manufacturing
Work:
Various
Home Educator, Community Volunteer, Student
Motorola 1999 - 2002
Senior Hardware Design Engineer
Hewlett-Packard 1994 - 1999
Hardware Design Engineer
1994 - 1999
Home Educator, Community Volunteer
Education:
Austin Community College 2013 - 2015
Purdue University 1992 - 1994
University of Maine 1990 - 1992
Masters, Electronics Engineering, Engineering, Electronics Missouri University of Science and Technology
Bachelors, Electronics Engineering, Electronics
Skills:
Verilog
Functional Verification
Java
Asic
Hardware Architecture
Static Timing Analysis
Microprocessors
Mixed Signal
Electronics
Algorithms
Powerpc
Image Processing
C
Embedded Systems
Teacher Mentoring
Ic
Debugging
Testing
Integrated Circuit Design
Semiconductors
Electrical Engineering
Programming
Peer Mentoring
Mentoring
Interests:
Sustainable Living
Economic Empowerment
Gardening
Nutrition
Education
Technology In Education
Environment
Reading
Hiking
Disaster and Humanitarian Relief
Certifications:
License Comp001020642648
1Z0-047 Oracle Database Sql Expert
Comptia Network Ce
Comptia, License Comp001020642648
Oracle

Business Records

Name / Title
Company / Classification
Phones & Addresses
Irene Heitsch
Director , Secretary
PRESTON OAKS OWNERS ASSOCIATION, INC
11149 Research Blvd STE 100, Austin, TX 78759

Publications

Us Patents

Image Rendition By Plural-Row Error Diffusion, For Faster Operation And Smaller Integrated Circuits

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US Patent:
59742283, Oct 26, 1999
Filed:
Jan 28, 1997
Appl. No.:
8/789859
Inventors:
Irene Heitsch - San Marcos CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
B41B 1500
G06K 936
G06K 938
H04N 104
US Classification:
395109
Abstract:
This system and method error-diffuse image data to generate printing decisions; scan and print stages are preferably included. Multiple image-data rows are held in longterm memory, usually external to an integrated circuit that does the processing; preferably data from plural rows at a time are received from that memory. Error from earlier-processed data is also held in longterm memory and fed to the circuit. Longterm-memory access is shared with many other functions; the invention keeps error diffusion from dominating that access. Processing preferably proceeds generally transverse (preferably skewed, ideally at 45. degree. ) to data rows, with final error distribution into each pixel when it is the "left pixel" (or when it is the "next pixel" if it is at the top of a row group). For pixels at the top of each run, the circuit retrieves error from, and for pixels at the bottom the circuit deposits error into, longterm memory; for intermediate pixels the circuit does neither--thus amortizing each data access over several pixels. Preferably plural rows are preprocessed to impart a skewed structure and also insert dummy pixels at corners (to simplify repetitive processing)--ideally with data and dummy pixels together forming a parallelogram, the dummy pixels being outboard at both sides of the data.
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Irene A Heitsch from Austin, TX, age ~63 Get Report