Search

Ibraz H Mohammed

from Fremont, CA
Age ~44
Get Report
Also known as:
Ibraz Mohemmed, Mohammed Ibraz, Mohemmed Ibraz
Phone and address:
4442 Delaware Dr, Fremont, CA 94538
Related to:
Liaqat Ali Syed, 65Mohammed Mukaram, 57
Connected to:
Abas K Mohammed, 63Abbas A Mohammed, 44Abdallah K Mohammed, 67Abdo H Mohammed, 56Abdulrahman Mohammed, 43Abdus S Mohammed, 45Aja Mohammed, 38Akil Mohammed, 99Alec C Mohammed, 32Alina S Mohammed, 27

Ibraz Mohammed Phones & Addresses

  • 4442 Delaware Dr, Fremont, CA 94538
  • San Jose, CA
  • 936 Terrace Rd, Tempe, AZ 85281 (480) 894-0546
  • 919 Lemon St, Tempe, AZ 85281 (480) 894-0546

Resumes

Resumes

Ibraz Mohammed Photo 1

Ibraz Mohammed

View page
Location:
4442 Delaware Dr, Fremont, CA 94538
Industry:
Computer Software
Skills:
Eda
Algorithms
Tcl
Software Engineering
C++
Debugging
C
Unix
Software Development
Data Structures
Shell Scripting
Linux
Distributed Systems
Object Oriented Design
Multithreading
Java
Languages:
English
Ibraz Mohammed Photo 2

Ibraz Mohammed

View page

Publications

Us Patents

Placer With Wires For Rf And Analog Design

View page
US Patent:
7603642, Oct 13, 2009
Filed:
Sep 27, 2006
Appl. No.:
11/528235
Inventors:
Pero Subasic - Santa Clara CA, US
Xuejin Wang - Chandler AZ, US
Enis A. Dengi - Tempe AZ, US
Ibraz H. Mohammed - Tempe AZ, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 10, 716 12, 716 14
Abstract:
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.

Integrated Synthesis Placement And Routing For Integrated Circuits

View page
US Patent:
7356784, Apr 8, 2008
Filed:
Dec 6, 2004
Appl. No.:
11/006323
Inventors:
Enis Aykut Dengi - Tempe AZ, US
Stephen McCracken - Tempe AZ, US
Michael R. Kelly - Gibsonia PA, US
Matthew B. Phelps - Pittsburgh PA, US
Ibraz Mohammed - Tempe AZ, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 4, 716 7, 716 10, 716 13
Abstract:
A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from the one or more device variables and the one or more weights; and determining the IC design from the one or more device variables and the one or more net lengths. The IC design includes a schematic and a layout. The process can be repeated as needed according to performance criteria that may include circuit performance metrics and layout performance metrics.
Control profile
Ibraz H Mohammed from Fremont, CA, age ~44 Get Report