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Hui Pan

from San Gabriel, CA
Age ~66
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Also known as:
Hsiu Pan, Pan Hui, Rajasekhar Athunuri, Peter Perez
Phone and address:
1328 Prospect Ave APT C, San Gabriel, CA 91776
Related to:
Christina Chen, 66Tin Fon LinJohn Nguyen, 64Ivy A Chu, 65Ngar C Hung, 74Peter H Hung, 66
Connected to:
Addison M Pan, 53Alexander L Pan, 51Andre Pan, 29Barry Pan, 72Bernice Pan, 99Boris Pan, 35Braden C Pan, 39Caroline C Pan, 68Chan S Pan, 42Chester C Pan, 61

Hui Pan Phones & Addresses

  • 1328 Prospect Ave APT C, San Gabriel, CA 91776
  • Ontario, CA
  • 800 Chapel Ave, Alhambra, CA 91801 (626) 570-8739
  • 4939 La Madera Ave, El Monte, CA 91732 (626) 444-4354
  • 53 Fano St, Arcadia, CA 91006 (626) 446-2378
  • Walnut, CA
  • Chino, CA
  • Boca Raton, FL
  • Los Angeles, CA

Resumes

Resumes

Hui Pan Photo 1

Hui Pan

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Hui Pan Photo 2

Hui Pan

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Hui Pan Photo 3

Project Manager

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Work:

Project Manager
Education:
中国传媒大学Communication University of China (Cuc)
Hui Pan Photo 4

Market Research Professional

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Location:
Greater Los Angeles Area
Industry:
Market Research

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hui Pan
Xt 66016
Broadcom Corporation
Semiconductors and Related Devices
5300 California Ave, Irvine, CA 92617
Hui Pan
Xt 66016
Broadcom Corporation
Semiconductors and Related Devices
5300 California Ave, Irvine, CA 92617
Hui Wen Pan
M
Expert International Investment LLC
8544 Larkdale Rd, San Gabriel, CA 91775

Publications

Us Patents

Delay Equalized Z/2Z Ladder For Digital To Analog Conversion

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US Patent:
7042381, May 9, 2006
Filed:
Jan 13, 2005
Appl. No.:
11/034052
Inventors:
Hui Pan - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 1/78
US Classification:
341154, 341153
Abstract:
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.

Method And System For A Glitch-Free Differential Current Steering Switch Circuit For High Speed, High Resolution Digital-To-Analog Conversion

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US Patent:
7071858, Jul 4, 2006
Filed:
Jun 30, 2005
Appl. No.:
11/169665
Inventors:
Hui Pan - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 1/00
US Classification:
341133, 341136, 341144, 341153, 341154, 327359, 330252, 330253
Abstract:
Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.

Delay Equalized Z/2Z Ladder For Digital To Analog Conversion

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US Patent:
7132970, Nov 7, 2006
Filed:
Mar 16, 2005
Appl. No.:
11/080808
Inventors:
Hui Pan - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 1/78
US Classification:
341154, 341153
Abstract:
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.

System For Shifting Data Bits Multiple Times Per Clock Cycle

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US Patent:
7583772, Sep 1, 2009
Filed:
Oct 3, 2005
Appl. No.:
11/240678
Inventors:
Hui Pan - Irvine CA, US
Seong-Ho Lee - Aliso Viejo CA, US
Michael Q. Le - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
US Classification:
375372, 375371, 375259, 375354, 375355
Abstract:
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

Hierarchical Parallel Pipelined Operation Of Analog And Digital Circuits

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US Patent:
20060066466, Mar 30, 2006
Filed:
Sep 24, 2004
Appl. No.:
10/948547
Inventors:
Hui Pan - Irvine CA, US
Ichiro Fujimori - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 1/38
US Classification:
341161000
Abstract:
A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Method For Shifting Data Bits Multiple Times Per Clock Cycle

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US Patent:
20090296868, Dec 3, 2009
Filed:
Aug 5, 2009
Appl. No.:
12/536186
Inventors:
Hui PAN - Irvine CA, US
Seong-Ho Lee - Aliso Viejo CA, US
Michael Q. Le - Laguna Niguel CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H04L 7/00
US Classification:
375372
Abstract:
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

System And Method For Power Control In A Physical Layer Device

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US Patent:
20130268782, Oct 10, 2013
Filed:
Apr 13, 2012
Appl. No.:
13/446454
Inventors:
Derek Tam - Irvine CA, US
Xin Wang - Tustin CA, US
Hui Pan - Irvine CA, US
Joseph Aziz - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 1/26
G06F 1/32
US Classification:
713310
Abstract:
A system and method for power control in a physical layer device. Energy savings during an active state can be produced through the monitoring of a received signal level by a receiver in a physical layer device. In one embodiment, based on an indication of the received signal level or other communication characteristic of the transmission medium, a control module can adjust the signal level or amplitude and/or adjust the voltage supply.

Power-Efficient Driver Architecture

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US Patent:
20130294294, Nov 7, 2013
Filed:
May 7, 2012
Appl. No.:
13/465216
Inventors:
Hui Pan - Irvine CA, US
Yuan Yao - Irvine CA, US
Joseph Aziz - Irvine CA, US
Derek Tam - Irvine CA, US
Xin Wang - Tustin CA, US
Chia-Jen Hsu - Irvine CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H04B 1/56
US Classification:
370276
Abstract:
Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid.
Control profile
Hui Pan from San Gabriel, CA, age ~66 Get Report