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Helena Stadniychuk Phones & Addresses

  • 1696 Galway Ln, Saint Paul, MN 55122
  • Eagan, MN
  • 814 8Th St SE, Minneapolis, MN 55414
  • Bloomington, MN
  • Madison, WI

Publications

Us Patents

Fabrication Of Multi-Dimensional Microstructures

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US Patent:
8313659, Nov 20, 2012
Filed:
Jul 10, 2009
Appl. No.:
12/501372
Inventors:
Helena Pavlovna Stadniychuk - Eagan MN, US
Andrew David Habermas - Bloomington MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01B 13/00
B32B 3/00
C25D 5/02
C25D 7/00
US Classification:
216 13, 428172, 205118, 205122
Abstract:
A method for forming a multi-dimensional microstructure, such as but not limited to a three dimensional (3-D) microstructure coil for use in a data transducer of a data storage device. In accordance with some embodiments, the method generally includes providing a base region comprising a first conductive pathway embedded in a first dielectric material; etching a plurality of via regions in the first dielectric material that are each partially filled with a first seed layer that contacts the embedded first conductive pathway; and using the first seed layer to form a conductive pillar in each of the plurality of via regions, wherein each conductive pillar comprises a substantially vertical sidewall that extends to a first distance above the base region.

Cell Patterning With Multiple Hard Masks

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US Patent:
20100327248, Dec 30, 2010
Filed:
Jun 29, 2009
Appl. No.:
12/493281
Inventors:
Antoine Khoueir - Apple Valley MN, US
Shuiyuan Huang - Apple Valley MN, US
Andrew Habermas - Bloomington MN, US
Helena Stadniychuk - Eagan MN, US
Ivan P. Ivanov - Apple Valley MN, US
Yongchul Ahn - Eagan MN, US
Assignee:
SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:
H01L 47/00
US Classification:
257 2, 438 3, 438478, 257E47001, 257E47005
Abstract:
A method of making a memory cell or magnetic element by using two hard masks. The method includes first patterning a second hard mask to form a reduced second hard mask, with a first hard mask being an etch stop for the patterning process, and then patterning the first hard mask to form a reduced first hard mask by using the reduced second hard mask as a mask and using an etch stop layer as an etch stop. After patterning both hard masks, then patterning a functional layer by using the reduced first hard mask as a mask. In the resulting memory cell, the first hard mask layer is also a top lead, and the diameter of the first hard mask layer is at least essentially the same as the diameter of the etch stop layer, the adhesion layer, and the functional layer.

Etching Nitride And Anti-Reflective Coating

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US Patent:
7915175, Mar 29, 2011
Filed:
Jun 27, 2005
Appl. No.:
11/169152
Inventors:
Saurabh Dutta Chowdhury - Dallas TX, US
Helena Stadniychuk - Eagan MN, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/461
H01L 21/302
US Classification:
438724, 438725, 257E21214
Abstract:
A method of forming a semiconductor structure comprises etching an anti-reflective coating on a substrate with a first plasma comprising bromine and oxygen; and etching a nitride layer on the substrate with a second plasma comprising bromine and oxygen.
Helena P Stadniychuk from Saint Paul, MN, age ~54 Get Report