Hong Lin Chang

7492005, Feb 17, 2009

Dec 28, 2005

11/321957

Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US

Alpha & Omega Semiconductor, Ltd. - Hamilton

H01L 29/76

257330, 257340

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

7632733, Dec 15, 2009

Apr 29, 2006

11/413248

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/336

438270, 257E2153

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

7667264, Feb 23, 2010

Sep 27, 2004

10/952231

Tiesheng Li - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
Hong Chang - Cupertino CA, US
Moses Ho - Campbell CA, US

Alpha and Omega Semiconductor Limited - Sunnyvale CA

H01L 29/94

257330, 257329, 257331, 257E29257, 257E2926

A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

7767526, Aug 3, 2010

Jan 29, 2009

12/362414

Yeeheng Lee - San Jose CA, US
Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
John Chen - Palo Alto CA, US
Anup Bhalla - Santa Clara CA, US

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/336

438268, 438206, 438209, 438212, 257E29262

Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

7875541, Jan 25, 2011

Dec 22, 2009

12/655162

Tiesheng Li - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
Hong Chang - Cupertino CA, US
Moses Ho - Campbell CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/3205

438589, 438259, 438270, 438585, 438595, 257330, 257E29257, 257E21626, 257E2164

Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening.

7879676, Feb 1, 2011

Jul 30, 2010

12/847863

Yeeheng Lee - San Jose CA, US
Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
John Chen - Palo Alto CA, US
Anup Bhalla - Santa Clara CA, US

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/336

438268, 438206, 438209, 438212, 257E29262

Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

7910486, Mar 22, 2011

Jun 12, 2009

12/484166

Hamza Yilmaz - Saratoga CA, US
Xiaobin Wang - San Jose CA, US
Anup Bhalla - Santa Clara CA, US
John Chen - Palo Alto CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/311

438700, 438246, 438389, 438510, 438692, 257E21042, 257E21943, 257E21051, 257E21077, 257E21267, 257E21304, 257E21435, 257E21545, 257E21546, 257E21562

A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

7928507, Apr 19, 2011

Dec 9, 2009

12/653130

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 29/66
H01L 29/06

257330, 257622, 257E2153, 257E21585

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.