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Hans Greub Phones & Addresses

  • North Plains, OR
  • Cornelius, OR
  • 182 Delaware Ave, Troy, NY 12180
  • Hillsboro, OR
  • Watervliet, NY
  • Vancouver, WA

Publications

Us Patents

Method And Apparatus For Fully Automated Signal Integrity Analysis For Domino Circuitry

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US Patent:
6836755, Dec 28, 2004
Filed:
Dec 30, 1999
Appl. No.:
09/475717
Inventors:
Mark D. Nardin - Portland OR
Hans Greub - Cornelius OR
Sapumal Wijeratne - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1750
US Classification:
703 13, 716 4, 716 5, 716 6
Abstract:
In one embodiment, the invention is a method. The method includes extracting parameters of a set of domino logic circuits. The method also includes simulating each domino logic circuit of the set of domino logic circuits. Also, the method includes reporting results of the simulation.

Keeper Circuit

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US Patent:
8362806, Jan 29, 2013
Filed:
Jun 26, 2009
Appl. No.:
12/459113
Inventors:
Sapumal B. Wijeratne - Portland OR, US
Clifford L. Ong - Portland OR, US
Hans J. Greub - North Plains OR, US
Anandraj Devarajan - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/096
US Classification:
326 95, 326 98
Abstract:
Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Apparatus For Skew Compensating Signals

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US Patent:
48336955, May 23, 1989
Filed:
Sep 8, 1987
Appl. No.:
7/093930
Inventors:
Hans J. Greub - Troy NY
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H04L 700
US Classification:
375118
Abstract:
A clock signal is transmitted to nodes of each of several interconnected circuits through a separate adjustable delay circuit, the time delay of each delay circuit being adjusted so that the clock signal arrives at each node at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor. The delay element monitor measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.

Method For Analyzing And Efficiently Reducing Signal Cross-Talk Noise

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US Patent:
61287695, Oct 3, 2000
Filed:
Dec 31, 1997
Appl. No.:
9/001257
Inventors:
Roy Carlson - Hillsboro OR
Hans J. Greub - Cornelius OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 6
Abstract:
In the present invention, a method is provided for analyzing signal noise caused by cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. This method comprises selecting the victim signal, selecting the attacker signal, performing cross-talk attacker filtering on a plurality of signal lines to identify a first set of potential attacker signals on a first set of potential attacker signal lines that cause signal noise upon said victim signal, performing safety window filtering on a plurality of signals signal lines to identify a second set of potential attacker signals on a second set of potential attacker signal lines that cause signal noise upon the victim signal line, and reducing the effects of the signal noise on at least one of the victim signal lines.

Multiple Lead Probe For Integrated Circuits In Wafer Form

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US Patent:
49123998, Mar 27, 1990
Filed:
Jun 9, 1987
Appl. No.:
7/059903
Inventors:
Hans J. Greub - Troy NY
Valdis E. Garuts - Beaverton OR
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
G01R 102
G01R 104
US Classification:
324158P
Abstract:
A probe assembly for use in conveying signals between cables from test apparatus and contact areas on a contact face of an integrated circuit includes a support member having an aperture therein and a dielectric membrane clamped over the aperture such that conductive bumps mounted on the underside of the periphery of the membrane engage corresponding contact areas on an upper surface of the support member surrounding the aperture. A central area of the membrane extends downward through the aperture such that conductive bumps on the under side of the central area of the membrane engage contact areas on the contact face of an integrated circuit situated below the aperture. A plurality of conductor runs supported by the membrane extend from the conductive bumps in the central area of the membrane to the conductive bumps in the periphery of the membrane. A plurality of second conductor runs supported by the support member extend from the contact areas surrounding the aperture to test apparatus cable connectors adjacent to the periphery of the support member.

Method For Analyzing And Efficiently Eliminating Timing Problems Induced By Cross-Coupling Between Signals

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US Patent:
59830069, Nov 9, 1999
Filed:
Dec 31, 1997
Appl. No.:
9/001407
Inventors:
Roy Carlson - Hillsboro OR
Hans J. Greub - Cornelius OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1124
US Classification:
39550005
Abstract:
This invention illustrates a method is provided for analyzing cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. The method in this invention comprises the acts of selecting the victim signal, selecting the attacker signal, performing timing filtering upon a number of signal lines in order to identify a set of potential attacker signals, performing logic filtering upon a number of signal lines to identify a second set of potential attacker signals, and reducing the effects of the cross-coupling between the attacker signal line and the victim signal line.

Multiple Port Random Access Memory

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US Patent:
48336491, May 23, 1989
Filed:
Sep 8, 1987
Appl. No.:
7/093931
Inventors:
Hans J. Greub - Troy NY
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
G11C 700
US Classification:
36518906
Abstract:
A multiple port memory includes a set of memory units each comprising a set of memory cells, one corresponding to each port. Each cell of a memory unit stores a single data bit and each cell is independently read and write accessed through separate data, address and control busses. The cells of each memory unit are cross-coupled so that when the state of the bit stored by one of the cells of a memory unit is changed when write accessed, the other cells of the memory unit thereafter change the states of their stored bits in the same way.
Hans J Greub from North Plains, OR, age ~65 Get Report