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Haluk Konuk Konuk

from Palo Alto, CA
Age ~59
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Also known as:
Haluk A Konuk, Haluk C Konuk, Haluk Kohuk, Haluk Konk, Konuk Haluk
Phone and address:
2280 Saint Francis Dr, Palo Alto, CA 94303
(408) 396-4593
Connected to:
Sertac Konuk, 50Dincer Konur, 39Henry A Konuwa, 31Diane L Konvalina, 63Tiffany L Konvalin, 50Judy L Konves, 62Tricia S Konves, 50Cherie D Konvicka, 66Sara I Konvitz, 44Susan M Konvolinka, 68

Haluk Konuk Phones & Addresses

  • 2280 Saint Francis Dr, Palo Alto, CA 94303 (408) 396-4593
  • 249 Ferndale Ave, Sunnyvale, CA 94085 (408) 734-5877
  • Redwood City, CA
  • Mountain View, CA
  • Pittsburg, CA
  • Santa Cruz, CA
  • Capitola, CA

Work

Company: Broadcom Nov 2000 Position: Technical director

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Santa Cruz 1991 to 1995 Specialities: Electrical Engineering

Skills

Asic • Soc • Semiconductors • Verilog • Simulations • Ic • Vlsi • Perl • Embedded Systems • Debugging • Dft • Application Specific Integrated Circuits • System on A Chip • Very Large Scale Integration • Integrated Circuits

Emails

h***[email protected]

Industries

Semiconductors

Resumes

Resumes

Haluk Konuk Photo 1

Technical Director

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Broadcom
Technical Director
Agilent Technologies 1999 - 2000
Technical Contributor
Opelin 1995 - 2000
Technical Contributor
Education:
University of California, Santa Cruz 1991 - 1995
Doctorates, Doctor of Philosophy, Electrical Engineering Case Western Reserve University 1987 - 1989
Master of Science, Masters, Electronics Engineering Boğaziçi University 1982 - 1986
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Asic
Soc
Semiconductors
Verilog
Simulations
Ic
Vlsi
Perl
Embedded Systems
Debugging
Dft
Application Specific Integrated Circuits
System on A Chip
Very Large Scale Integration
Integrated Circuits

Publications

Us Patents

Integrated Circuit With Scan Flip-Flop

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US Patent:
6380780, Apr 30, 2002
Filed:
Jun 1, 2000
Appl. No.:
09/585366
Inventors:
Robert C. Aitken - San Jose CA
Haluk Konuk - Mountain View CA
Jeff Rearick - Fort Collins CO
John Stephen Walther - Sunnyvale CA
Assignee:
Agilent Technologies, Inc - Palo Alto CA
International Classification:
H03K 3356
US Classification:
327202, 327203
Abstract:
An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing.

Clock Multiplier Using Masked Control Of Clock Pulses

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US Patent:
6756827, Jun 29, 2004
Filed:
Sep 11, 2002
Appl. No.:
10/241070
Inventors:
Haluk Konuk - Sunnyvale CA
Vincent R. von Kaenel - Palo Alto CA
Dai M. Le - San Jose CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B 1900
US Classification:
327116, 327121, 327291
Abstract:
A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of a clock control signal used for masking. The clock multiplier circuit includes an oscillator, a storage device for synchronization of the masking signal to the pulses and a logic circuit to generate the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the output clock signal in response to the clock control signal, while other pulses are masked.

Row-Column Repair Technique For Semiconductor Memory Arrays

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US Patent:
6771549, Aug 3, 2004
Filed:
Feb 26, 2003
Appl. No.:
10/374921
Inventors:
Haluk Konuk - Sunnyvale CA
Zongbo Chen - San Jose CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 700
US Classification:
365200, 36518907
Abstract:
A method for locating a repair solution for a memory that includes a memory array containing a plurality of rows and a plurality of columns, N redundant rows, and M redundant columns. Both N and M are integers, where N is greater than or equal to zero and M is greater than or equal to zero. The N redundant rows and the M redundant columns are collectively referred to as redundant lines. The method includes generating a first defect matrix defects in the memory array. Additionally, the method includes recursively, until either the repair solution is found or the redundant lines are consumed: selecting a first line in the defect matrix and having at least one defect; generating a second defect matrix by eliminating at least the defects in the first line from the first defect matrix; and determining if the repair solution is found.

Clock Multiplier Using Masked Control Of Clock Pulses

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US Patent:
6914459, Jul 5, 2005
Filed:
Jun 1, 2004
Appl. No.:
10/857817
Inventors:
Haluk Konuk - Sunnyvale CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Dai M. Le - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B019/00
US Classification:
327116, 327291
Abstract:
A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of the clock input signal. The clock multiplier circuit includes an oscillator and a logic circuit which generates a control signal for synchronization of the pulses to the control signal and to mask the pulses after a selected number of pulses have been output as the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the clock output signal in response to the control signal, while other pulses are masked.

Row-Column Repair Technique For Semiconductor Memory Arrays

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US Patent:
6940766, Sep 6, 2005
Filed:
Jul 2, 2004
Appl. No.:
10/884658
Inventors:
Haluk Konuk - Sunnyvale CA, US
José L. Landivar - Sunnyvale CA, US
Zongbo Chen - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C029/00
US Classification:
365200, 36518907, 714733
Abstract:
A method for locating a repair solution for a memory that includes a memory array comprising a plurality of rows and a plurality of columns, N redundant rows, and M redundant columns is described. Both N and M are integers, where N is greater than or equal to zero and M is greater than or equal to zero. The N redundant rows and the M redundant columns are collectively referred to as redundant lines. The method includes generating a first defect matrix representing defects in the memory array. Additionally, the method includes recursively, until either the repair solution is found or the redundant lines are consumed: selecting a first line represented in the defect matrix and having at least one defect; generating a second defect matrix by eliminating at least the defects in the first line from the first defect matrix; and determining if the repair solution is found.

Implementation Of Test Patterns In Automated Test Equipment

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US Patent:
7065693, Jun 20, 2006
Filed:
Feb 13, 2004
Appl. No.:
10/778753
Inventors:
Haluk Konuk - Sunnyvale CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 11/00
US Classification:
714738, 714815
Abstract:
An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles during the timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in pattern memory for the timed test pattern. The method and apparatus of the present invention can be implemented to test integrated circuits comprising circuitry operating in first and second time domains wherein the first and second timing intervals of the timed test pattern correspond to the first and second time domains of the circuit, respectively.

Circuit For Pll-Based At-Speed Scan Testing

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US Patent:
7380189, May 27, 2008
Filed:
Jun 15, 2004
Appl. No.:
10/868546
Inventors:
Haluk Konuk - Sunnyvale CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G01R 31/28
US Classification:
714731, 714729
Abstract:
A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an integrated circuit. When the integrated circuit is under at-speed scan test mode of operation, the clock generation circuit receives a scan-clock signal to scan in a test vector to the scannable flip-flops during an input shift phase when shifting is enabled and to scan out a resultant vector from the scannable flip-flops during an output shift phase when shifting is also enabled. However, when shifting is not enabled during a capture phase between the two shift phases, the scan-clock signal triggers a 2-pulse circuit to release two pulses during the capture phase of at-speed scan testing. The two pulses from the 2-pulse circuit are based on an internal PLL-based clock signal. The clock generation circuit may be utilized in single or multiple clock domain systems.

Programmable Frequency Multiplier

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US Patent:
20050218957, Oct 6, 2005
Filed:
Jun 7, 2005
Appl. No.:
11/146566
Inventors:
Haluk Konuk - Sunnyvale CA, US
Vincent von Kaenel - Palo Alto CA, US
Dai Le - San Jose CA, US
International Classification:
H03B019/00
US Classification:
327316000
Abstract:
In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.
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Haluk Konuk Konuk from Palo Alto, CA, age ~59 Get Report