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Guy Moffat Phones & Addresses

  • 4902 Bentbrook Dr, Manlius, NY 13104 (315) 682-8508
  • Palo Alto, CA
  • 2511 Betlo Ave, Mountain View, CA 94043 (650) 964-0462
  • New York, NY

Emails

g***t@aol.com

Business Records

Name / Title
Company / Classification
Phones & Addresses
Guy Moffat
Owner
Cmj Machining Co
Mfg Industrial Machinery · Mfg Misc Fabricated Metal Products · Metal Restoration
5124 Calle Del Sol, Santa Clara, CA 95054
(408) 982-9373, (408) 982-9508, (408) 586-8822

Publications

Us Patents

Power Savings With Multiple Readout Circuits

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US Patent:
7619669, Nov 17, 2009
Filed:
Dec 29, 2003
Appl. No.:
10/745611
Inventors:
Sandor L. Barna - Pasadena CA, US
Guy Moffat - Manlius NY, US
Assignee:
Micron Technologies, Inc. - Boise ID
International Classification:
H04N 3/14
US Classification:
348283, 348321
Abstract:
An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within the column sample and hold circuitry; in another embodiment the switch is located between the column sample and hold circuitry and the readout chains. The switch circuit ensures that signals from the column sample and hold circuitry are directed to enabled readout chains, which allows selective enabling/disabling of readout chains. By disabling readout chains, the imager's power consumption is reduced.

Power Savings With Multiple Readout Circuits

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US Patent:
8314867, Nov 20, 2012
Filed:
Oct 21, 2009
Appl. No.:
12/603151
Inventors:
Sandor L. Barna - Pasadena CA, US
Guy Moffat - Manlius NY, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H04N 3/14
H04N 5/335
H04N 9/04
H04N 9/083
US Classification:
348283, 348323
Abstract:
An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within the column sample and hold circuitry; in another embodiment the switch is located between the column sample and hold circuitry and the readout chains. The switch circuit ensures that signals from the column sample and hold circuitry are directed to enabled readout chains, which allows selective enabling/disabling of readout chains. By disabling readout chains, the imager's power consumption is reduced.

Method And Apparatus For Providing A Configurable Display Memory For Single Buffered And Double Buffered Application Programs To Be Run Singly Or Simultaneously

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US Patent:
57427887, Apr 21, 1998
Filed:
Jun 27, 1994
Appl. No.:
8/266095
Inventors:
Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Bruce McIntyre - Cupertino CA
Guy Moffat - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1206
US Classification:
395437
Abstract:
An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Method And Apparatus For Increasing The Speed Of Operation Of A Double Buffered Display System

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US Patent:
55877265, Dec 24, 1996
Filed:
Oct 6, 1994
Appl. No.:
8/319474
Inventors:
Guy Moffat - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G09G 500
US Classification:
345201
Abstract:
An output display system including an output display; apparatus for controlling the writing of information to the output display; and a double buffered memory including a first bank of video random access memory for furnishing information to the output display, a second bank of video random access memory for furnishing information to the output display, and apparatus for addressing alternate banks of memory as each line of the output display in a frame is written.

Computer System With A Shared Address Bus And Pipelined Write Operations

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US Patent:
61417416, Oct 31, 2000
Filed:
Aug 29, 1996
Appl. No.:
8/705057
Inventors:
Curtis Priem - Fremont CA
Satyanarayana Nishtala - Cupertino CA
Michael G. Lavelle - Saratoga CA
Thomas Webber - Cambridge MA
Daniel E. Lenoski - San Jose CA
Peter A. Mehring - Sunnyvale CA
Guy Moffat - Mountain View CA
Christopher R. Owen - Los Gatos CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1200
US Classification:
711217
Abstract:
A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Method And Apparatus For Arranging Access Of Vram To Provide Accelerated Writing Of Vertical Lines To An Output Display

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US Patent:
51422760, Aug 25, 1992
Filed:
Dec 21, 1990
Appl. No.:
7/632040
Inventors:
Guy Moffat - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G09G 102
US Classification:
340799
Abstract:
An arrangement for writing to and reading from the random access ports of a multibank frame buffer so that individual pixels to be presented in a vertical line on an output display are arranged sequentially from top to bottom in different banks of the frame buffer.

Apparatus For Selecting Frame Buffers For Display In A Double Buffered Display System

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US Patent:
55438245, Aug 6, 1996
Filed:
Aug 28, 1995
Appl. No.:
8/520301
Inventors:
Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Bruce McIntyre - Cupertino CA
Guy Moffat - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G09G 102
US Classification:
345201
Abstract:
A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Method And Apparatus For Allowing Computer Circuitry To Function With Updated Versions Of Computer Software

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US Patent:
55772323, Nov 19, 1996
Filed:
Dec 22, 1994
Appl. No.:
8/363305
Inventors:
Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Bruce McIntyre - Cupertino CA
Guy Moffat - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 900
US Classification:
395500
Abstract:
An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.
Guy K Moffat from Manlius, NY, age ~61 Get Report