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Gopal Solanki

from San Jose, CA
Age ~63
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Also known as:
Goapal Solanki
Phone and address:
5621 Country Club Pkwy, San Jose, CA 95138
(408) 223-9242
Related to:
Rajiv S SolankiTarun SolankiMukta Solanki, 57
Connected to:
Aakash M Solanki, 33Abhishek D Solanki, 37Akshaykumar Solanki, 38Altaf H Solanki, 49Anil D Solanki, 86Avinash Solanki, 37Dharmendra S Solanki, 52Harsha Solanki, 68Hema B Solanki, 45Jasu V Solanki, 82

Gopal Solanki Phones & Addresses

  • 5621 Country Club Pkwy, San Jose, CA 95138 (408) 223-9242
  • 3146 Whitby Ct, San Jose, CA 95148 (408) 223-9242
  • Fair Oaks, CA
  • Sunnyvale, CA

Resumes

Resumes

Gopal Solanki Photo 1

Chief Executive Officer

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Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Magnum Semiconductor since Feb 2008
CEO
Gopal Solanki Photo 2

Gopal Solanki

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Gopal Solanki Photo 3

Gopal Solanki

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Gopal Solanki
Vice President
NVIDIA
Computer Hardware · Mfg Semiconductors/Related Devices & Custom Computer Programming · Mfg Semiconductors/Related Devices and Custom Computer Programming · Radio and Television Broadcasting and Wireless Communication · Semiconductor and Related Device Manufacturing · Custom Computer Programming Svcs · Semiconductor Devices (Manufac
2701 San Tomas Expy, Santa Clara, CA 95050
561 E Elliot Rd #195, Chandler, AZ 85225
3535 Monroe St, Santa Clara, CA 95051
2860 San Tomas Expy, Santa Clara, CA 95051
(408) 486-2000, (408) 980-8001, (408) 486-2200, (408) 486-8236

Publications

Us Patents

Graphics Pipeline Selectively Providing Multiple Pixels Or Multiple Textures

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US Patent:
6628290, Sep 30, 2003
Filed:
Oct 2, 2000
Appl. No.:
09/677941
Inventors:
David B. Kirk - San Francisco CA
Gopal Solanki - San Jose CA
Curtis Priem - Fremont CA
Walter Donovan - Milpitas CA
Joe L. Yeun - San Jose CA
Assignee:
nVidia Corporation - Santa Clara CA
International Classification:
G06T 120
US Classification:
345506, 345582, 345561
Abstract:
A method and graphics accelerator apparatus for pipelined generation of output values for a sequence of pixels, with generation of output values for each of at least two textured pixels during each pipeline clock interval. The apparatus includes a combiner stage capable of producing output values during each clock interval of the pipeline, wherein the output values are indicative of a blend of a plurality of textures with a single pixel when the combiner stage operates in a first mode, and the output values are indicative of a blend of an individual texture with two pixels when the combiner stage operates in a second mode.

Texture Caching Arrangement For A Computer Graphics Accelerator

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US Patent:
6919895, Jul 19, 2005
Filed:
Mar 22, 1999
Appl. No.:
09/273827
Inventors:
Gopal Solanki - San Jose CA, US
Kioumars Kevin Dawallu - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F015/16
US Classification:
345503, 345582, 345552, 345557
Abstract:
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Texture Cache For A Computer Graphics Accelerator

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US Patent:
7136068, Nov 14, 2006
Filed:
Apr 7, 1998
Appl. No.:
09/056656
Inventors:
Curtis Priem - Fremont CA, US
Gopal Solanki - San Jose CA, US
David Kirk - San Francisco CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 15/16
US Classification:
345503, 345531, 345537, 345552, 345559, 345568
Abstract:
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, and a cache for texels for use by the circuitry to generate texture value for any pixel.

Texture Caching Arrangement For A Computer Graphics Accelerator

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US Patent:
7330188, Feb 12, 2008
Filed:
Feb 2, 2004
Appl. No.:
10/770078
Inventors:
Gopal Solanki - San Jose CA, US
Kioumars Kevin Dawallu - Boulder CO, US
International Classification:
G06T 11/40
G09G 5/00
G06F 15/16
US Classification:
345552, 345582, 345557, 345503
Abstract:
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Texture Caching Arrangement For A Computer Graphics Accelerator

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US Patent:
8018467, Sep 13, 2011
Filed:
Jun 20, 2005
Appl. No.:
11/158638
Inventors:
Gopal Solanki - San Jose CA, US
Kioumars Kevin Dawallu - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 15/16
G06T 11/40
G09G 5/36
G09G 5/00
US Classification:
345582, 345503, 345552, 345557
Abstract:
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Graphics Pipeline Selectively Providing Multiple Pixels Or Multiple Textures

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US Patent:
61813524, Jan 30, 2001
Filed:
Mar 22, 1999
Appl. No.:
9/273826
Inventors:
David B. Kirk - San Francisco CA
Gopal Solanki - San Jose CA
Curtis Priem - Fremont CA
Walter Donovan - Milpitas CA
Joe L. Yeun - San Jose CA
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 120
G06T 1140
US Classification:
345506
Abstract:
A graphics accelerator pipeline including a combiner stage capable of producing output values during each clock interval of the pipeline which map a plurality of textures to a single pixel or an individual texture to two pixels.
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Gopal Solanki from San Jose, CA, age ~63 Get Report