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Giuseppina Rosa Conti

from Oakland, CA
Age ~66
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Also known as:
Giuseppina R Conti, Giuseppina Te Conti, Guiseppina R Conti, Guissepina R Conti
Phone and address:
5570 Harbord Dr, Oakland, CA 94618
(510) 594-0216
Related to:
Giuesppina Conti, 66
Connected to:
Alejandro Conti, 97Angela K Conti, 44Annette Conti, 75Arielle N Conti, 34Beatriz E Conti, 42Briana M Conti, 36Carlo E Conti, 65Carmela Conti, 95Cindy Conti, 64Claudio Conti, 62

Giuseppina Conti Phones & Addresses

  • 5570 Harbord Dr, Oakland, CA 94618 (510) 594-0216
  • 2211 San Rafael Ave, Santa Clara, CA 95051 (408) 260-7949
  • Jenner, CA
  • 5570 Harbord Dr, Oakland, CA 94618

Resumes

Resumes

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Giuseppina Conti

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Location:
United States

Publications

Us Patents

Method For Fabricating An Integrated Gate Dielectric Layer For Field Effect Transistors

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US Patent:
7601648, Oct 13, 2009
Filed:
Jul 31, 2006
Appl. No.:
11/496411
Inventors:
Thai Cheng Chua - Cupertino CA, US
Shankar Muthukrisnan - Plano TX, US
Johanes Swenberg - Los Gatos CA, US
Shreyas Kher - Campbell CA, US
Chikuang Charles Wang - San Jose CA, US
Giuseppina Conti - Oakland CA, US
Yuri Uritsky - Newark CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/31
US Classification:
438763, 438287, 257E21409
Abstract:
Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.

Method For Modifying Dielectric Characteristics Of Dielectric Layers

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US Patent:
20040180556, Sep 16, 2004
Filed:
Mar 11, 2003
Appl. No.:
10/387160
Inventors:
Kang-Lie Chiang - San Jose CA, US
Mahmoud Dahimene - Sunnyvale CA, US
Xiaoye Zhao - Mountain View CA, US
Yan Ye - Saratoga CA, US
Gerardo Delgadino - Santa Clara CA, US
Hoiman Hung - Cupertino CA, US
Li-Qun Xia - Santa Clara CA, US
Giuseppina Conti - Oakland CA, US
Assignee:
Applied Materials, Inc.
International Classification:
H01L021/31
H01L021/469
US Classification:
438/781000
Abstract:
A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Nitrogen Profile Engineering In Hi-K Nitridation For Device Performance Enhancement And Reliability Improvement

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US Patent:
20070049043, Mar 1, 2007
Filed:
Aug 23, 2005
Appl. No.:
11/209472
Inventors:
Shankar Muthukrishnan - San Jose CA, US
Rahul Sharangpani - Fremont CA, US
Tejal Goyani - Sunnyvale CA, US
Pravin Narwankar - Sunnyvale CA, US
Shreyas Kher - Campbell CA, US
Yi Ma - Santa Clara CA, US
Giuseppina Conti - Oakland CA, US
International Classification:
H01L 21/31
US Classification:
438758000
Abstract:
A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.

Method Of Clustering Sequential Processing For A Gate Stack Structure

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US Patent:
20080119057, May 22, 2008
Filed:
Nov 20, 2006
Appl. No.:
11/561870
Inventors:
THAI CHENG CHUA - Cupertino CA, US
Christopher Sean Olsen - Fremont CA, US
Cory Czarnik - Saratoga CA, US
Giuseppina Conti - Oakland CA, US
International Classification:
H01L 21/31
US Classification:
438763, 257E2124
Abstract:
A method of forming a gate dielectric comprising silicon and oxygen is provided. The gate dielectric may also include nitrogen or another high k material. In one aspect, forming the gate dielectric includes annealing a substrate in an oxidizing atmosphere to form a silicon oxide layer, depositing a silicon nitride layer or a high k layer on the silicon oxide layer by a vapor deposition, oxidizing an upper surface of the silicon nitride layer or high k layer, and then annealing the substrate. The gate dielectric may be formed within an integrated processing system.
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Giuseppina Rosa Conti from Oakland, CA, age ~66 Get Report