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Giorgos S Tsapepas

from Chappaqua, NY
Age ~41
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Also known as:
Giongos Tsapepas, Tsapepas Giorgos
Phone and address:
35 Mayberry Rd, Chappaqua, NY 10514
(646) 559-4520
Related to:
Monica J Keyes, 60Blondell T Jones, 81Stelios G Tsapepas, 72Demetra S Tsapepas, 42Jonathan A Sucato, 46Tani D Tsapepas, 71Demetrios N BazasThyrza A Sucato, 80Stelios G Tsapepas, 71Tara J Sucato, 43Anastasia Bazas, 97Christopher A Sucato, 48
Connected to:
Yuliya Tsaplina, 51John M Tsapos, 62Brandon Tsaptsinos, 39Nezi Y Tsar, 60Geoffrey Tsaras, 51Alexei Tsaregorodtsev, 50Aleksandr M Tsarenko, 49Yevgeniy Tsarev, 60Yuri A Tsarev, 62Jessica Tsarfin, 27

Giorgos Tsapepas Phones & Addresses

  • 35 Mayberry Rd, Chappaqua, NY 10514 (646) 559-4520
  • 317 95Th St, New York, NY 10025 (646) 559-4520
  • 2712 Pine Cone Ct, Poughkeepsie, NY 12603
  • 7 Pineberry Ct, Poughkeepsie, NY 12603
  • Seattle, WA
  • Wappingers Fl, NY
  • Westchester, NY

Work

Company: Ibm Jan 2014 Position: Global head for systems and technology group sales - citi integrated account

Education

School / High School: Rensselaer Polytechnic Institute- Troy, NY 2001 Specialities: BS in Electrical Engineering

Skills

Large Deal Management • Global Team Integration • Sales Leadership • C-Suite Client Management • Mainframe • Problem Solving

Languages

English • Greek

Ranks

Certificate: Financial Markets Maestro Program

Industries

Information Technology And Services

Resumes

Resumes

Giorgos Tsapepas Photo 1

Global Key Account Director, Citigroup

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Location:
New York, NY
Industry:
Information Technology And Services
Work:
IBM - IBM New York, NY since Jul 2010
IBM Global Enterprise Systems, Citigroup
Education:
Rensselaer Polytechnic Institute 2002 - 2005
B.S., Electrical Engineering
Skills:
Perl
Vlsi
Vhdl
Analysis
Business Development
C++
Computer Architecture
Linux
Circuit Design
Microprocessors
Computer Engineering
Microarchitecture
Mainframe
Solution Selling
Large Deals
Business Case
Debugging
Simulations
Program Management
Db2
C
Aix
Hardware
Enterprise Architecture
Asic
Enterprise Software
Testing
Algorithms
Cadence
Cloud Computing
Ibm Mainframe
Computer Hardware
Software As A Service
Integration
Data Center
Solution Architecture
It Strategy
Ibm Aix
Languages:
English
Greek
Certifications:
Financial Markets Maestro Program
Giorgos Tsapepas Photo 2

Giorgos Tsapepas New York, NY

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Work:
IBM

Jan 2014 to 2000
Global Head for Systems and Technology Group Sales - Citi Integrated Account
IBM
New York, NY
Jul 2010 to Jan 2014
Global Head for System z Sales - Citi Integrated Account
IBM
Poughkeepsie, NY
May 2009 to Jul 2010
Staff Engineer - System z Microprocessor Virtual Bring Up
IBM
Poughkeepsie, NY
Feb 2007 to Jul 2010
Staff Engineer - Hardware Characterization and Test
IBM
Poughkeepsie, NY
Jun 2005 to Jul 2010
System z Custom Circuit Design
IBM
Poughkeepsie, NY
Dec 2008 to Apr 2009
Staff Engineer - System z Array Hardware Characterization Lead
Education:
Rensselaer Polytechnic Institute
Troy, NY
2001 to 2005
BS in Electrical Engineering
Skills:
Large Deal Management, Global Team Integration, Sales Leadership, C-Suite Client Management, Mainframe, Problem Solving

Publications

Us Patents

Spare Gate Array Cell Distribution Analysis

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US Patent:
20080320430, Dec 25, 2008
Filed:
Jun 25, 2007
Appl. No.:
11/767542
Inventors:
Giorgos Stellos Tsapepas - Poughkeepsie NY, US
David A. Webber - Poughkeepsie NY, US
Michael Hemsley Wood - Poughkeepsie NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 11
Abstract:
A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.

Method For Custom Register Circuit Design

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US Patent:
20090064082, Mar 5, 2009
Filed:
Aug 27, 2007
Appl. No.:
11/845124
Inventors:
Giorgos S. Tsapepas - Poughkeepsie NY, US
Michael H. Wood - Poughkeepsie NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 18
Abstract:
A computer program product stored on machine readable media is disclosed. The computer program product includes machine executable instructions for implementing a method of automatically creating a custom register circuit with a Computer Aided Design (CAD) application. The method includes obtaining parameters of the custom register circuit via a graphical user interface, executing one or more custom functions using the obtained parameters, and creating a cell comprising the custom register circuit.
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Giorgos S Tsapepas from Chappaqua, NY, age ~41 Get Report