Search

Gianluca C Colli

from Mountain View, CA
Age ~59

Gianluca Colli Phones & Addresses

  • 1543 Fordham Ct, Mountain View, CA 94040 (650) 968-2271 (408) 242-4261
  • Santa Clara, CA
  • 763A Loma Verde Ave, Palo Alto, CA 94303
  • San Jose, CA
  • Sunnyvale, CA
  • 1543 Fordham Ct, Mountain View, CA 94040 (650) 387-1960

Work

Company: On semiconductor Mar 2016 Position: Vice president and general manager - commercial sensing division - intelligent sensing group

Education

Degree: Master of Business Administration, Masters School / High School: Stanford University Graduate School of Business 2007 to 2007 Specialities: Economics, Business

Skills

Analog • Analog Circuit Design • Semiconductor Industry • Semiconductors • Power Management • Ic • Team Leadership • Leadership • Circuit Design • Mixed Signal • Rf • Mobile Devices • System Design • Product Development • Pricing Strategy • Cmos • Integrated Circuits • Crm • Testing • Processors • Budgets • Product Engineering • Business Development • Electronics • Application Specific Integrated Circuits • Strategic Leadership • Product Marketing • Product Management • New Business Development • Marketing Strategy • Strategic Planning • Asic • Soc • Cross Functional Team Leadership

Languages

English • Italian

Emails

g***i@netscape.net

Industries

Semiconductors

Resumes

Resumes

Gianluca Colli Photo 1

Vice President And General Manager - Consumer Solutions Division

View page
Location:
1543 Fordham Ct, Mountain View, CA 94040
Industry:
Semiconductors
Work:
On Semiconductor
Vice President and General Manager - Commercial Sensing Division - Intelligent Sensing Group

Texas Instruments Feb 2014 - Feb 2016
General Manager - Mobile Device Power Division

Texas Instruments Sep 2011 - Feb 2014
Product Line Director, Mobile Lighting and Power Pl

National Semiconductor Jun 2009 - Sep 2011
Business Unit Director, User Experience, Mobile Device Power

National Semiconductor Jan 2008 - Jun 2009
Senior Director of Engineering, Mobile Device Power
Education:
Stanford University Graduate School of Business 2007 - 2007
Master of Business Administration, Masters, Economics, Business
Università Di Pavia 1991 - 1991
Masters, Electronics Engineering
Università Di Pavia 1984 - 1991
Bachelors, Bachelor of Science In Electrical Engineering, Electronics
Skills:
Analog
Analog Circuit Design
Semiconductor Industry
Semiconductors
Power Management
Ic
Team Leadership
Leadership
Circuit Design
Mixed Signal
Rf
Mobile Devices
System Design
Product Development
Pricing Strategy
Cmos
Integrated Circuits
Crm
Testing
Processors
Budgets
Product Engineering
Business Development
Electronics
Application Specific Integrated Circuits
Strategic Leadership
Product Marketing
Product Management
New Business Development
Marketing Strategy
Strategic Planning
Asic
Soc
Cross Functional Team Leadership
Languages:
English
Italian

Publications

Us Patents

Low-Voltage, Very-Low-Power Conductance Mode Neuron

View page
US Patent:
RE41658, Sep 7, 2010
Filed:
Jul 31, 2003
Appl. No.:
10/631323
Inventors:
Vito Fabbrizio - Piacenza, IT
Gianluca Colli - Santa Clara CA, US
Alan Kramer - Berkeley CA, US
Assignee:
STMicroelectronics S.r.l.
International Classification:
G06G 7/00
G06N 3/00
G06N 3/02
G06E 1/00
G06E 3/00
G06F 15/16
US Classification:
706 39, 706 15
Abstract:
A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Switching Voltage Regulator Having A Charge Pump Circuit

View page
US Patent:
59630256, Oct 5, 1999
Filed:
Dec 19, 1997
Appl. No.:
8/994738
Inventors:
Gianluca Colli - Santa Clara CA
Assignee:
STMicroelectronics, Inc. - Carrollton TX
International Classification:
G05F 1575
US Classification:
323288
Abstract:
A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I. sub. bias). The bias current (I. sub. bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4. sub. beta and mirrored again by a factor "c" on the output of DMOS2. The same I. sub. bias is mirrored by a ratio "b" and multiplied by the product of Q5. sub. beta and Q6. sub. beta. The push-pull current operation at the output terminal (416) is obtained by turning on and off switches SW1 (418) and SW2 (420) that are controlled by a clock signal. The voltage regulator (400) further includes an output voltage clamp (424) that keeps control of the V. sub. boost voltage by controlling the amount of bias current (I. sub. bias).

Bemf Rectification During Power Off To Prevent Parasitic Effect

View page
US Patent:
58834796, Mar 16, 1999
Filed:
Jul 1, 1997
Appl. No.:
8/886324
Inventors:
Paolo Menegoli - Milpitas CA
Gianluca Colli - Santa Clara CA
Assignee:
STMicroelectronics, Inc. - Carrollton TX
International Classification:
H02P 602
US Classification:
318254
Abstract:
A circuit and method to clamp a node of a power device connected to a driving node of a polyphase d-c motor to a reference potential during a powering off of the drive includes a current mirror and a comparator. A first input of the comparator is connected to the reference potential, and a second input is connected to the driving node. The reference potential may be a ground potential, or, preferably, the potential at another driving node of the motor. An output of the comparator is connected to a first side of the current mirror. A circuit is connected to apply a current reflecting the output of the comparator to a low side driver connected to the node.

Low-Voltage, Very-Low-Power Conductance Mode Neuron

View page
US Patent:
62693522, Jul 31, 2001
Filed:
Dec 14, 1999
Appl. No.:
9/461674
Inventors:
Vito Fabbrizio - Piacenza, IT
Gianluca Colli - Santa Clara CA
Alan Kramer - Berkeley CA
Assignee:
STMicroelectronics S.r.l. - Agrate Brianza
International Classification:
G06F 1518
US Classification:
706 15
Abstract:
A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Driver Circuit Including Preslewing Circuit For Improved Slew Rate Control

View page
US Patent:
57421935, Apr 21, 1998
Filed:
Oct 24, 1996
Appl. No.:
8/740195
Inventors:
Gianluca Colli - Santa Clara CA
Massimiliano Brambilla - San Jose CA
Assignee:
SGS-THOMSON Microelectronics, Inc. - Carrollton TX
International Classification:
H03K 512
US Classification:
327170
Abstract:
A preslewing circuit to rapidly drop a voltage on the gate of a power device in a power stage has a combination of a bipolar transistor and CMOS transistors. The gate voltage is brought down by the preslewing circuit to a level at which an output voltage can begin to change. The combination has high conduction and can be integrated readily, with good internal isolation, in a small chip area, thus having qualities desirable for high performance, integrated, driver circuits.

Low-Power, Low-Voltage Four-Quadrant Analog Multiplier, Particularly For Neural Applications

View page
US Patent:
58050078, Sep 8, 1998
Filed:
Sep 27, 1996
Appl. No.:
8/721870
Inventors:
Gianluca Colli - Santa Clara CA
Assignee:
SGS-Thomson Microelectronics S.r.l. - Agrate Brianza
International Classification:
G06F 744
G06G 716
US Classification:
327356
Abstract:
A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i. e. , as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Driver Circuit Including Slew Rate Control System With Improved Voltage Ramp Generator

View page
US Patent:
58252185, Oct 20, 1998
Filed:
Oct 24, 1996
Appl. No.:
8/736524
Inventors:
Gianluca Colli - Santa Clara CA
Massimiliano Brambilla - San Jose CA
Assignee:
STMicroelectronics, Inc. - Carrollton TX
International Classification:
H03K 300
US Classification:
327112
Abstract:
A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver. It is optional to have two current sources for charging, also, where a first source with voltage and than a second source, in a basic current mirror, continues charging substantially to the supply voltage.

Low-Voltage, Very-Low-Power Conductance Mode Neuron

View page
US Patent:
60321407, Feb 29, 2000
Filed:
Oct 15, 1996
Appl. No.:
8/731426
Inventors:
Vito Fabbrizio - Piacenza, IT
Gianluca Colli - Santa Clara CA
Alan Kramer - Berkeley CA
Assignee:
STMicroelectronics S.r.l. - Agrate Brianza
International Classification:
G06F 1518
US Classification:
706 15
Abstract:
A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
Gianluca C Colli from Mountain View, CA, age ~59 Get Report