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Gianluca Boselli

from Plano, TX
Age ~57
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Also known as:
Gianluc Boselli, Gianluca Boselu, Gianluca Boseell, Gianluca I
Phone and address:
5305 Channel Isle Dr, Plano, TX 75093
(972) 407-1696
Connected to:
Christine M Boselli, 72Shauna M Boselli, 31Kathleen S Boselowitz, 60Ashley N Bosely, 33Carminn J Boseman, 51Charita R Boseman, 45Diana C Boseman, 65Glenn H Boseman, 79Joyce N Boseman, 42Ronald Boseman, 68

Gianluca Boselli Phones & Addresses

  • 5305 Channel Isle Dr, Plano, TX 75093 (972) 407-1696
  • 4000 Parkside Center Blvd, Dallas, TX 75244 (972) 386-5588
  • Richardson, TX
  • Colton, TX

Work

Company: Texas instruments Sep 2011 Position: Analog esd lab manager

Education

Degree: Ph.D. School / High School: Twente University 1997 to 2000 Specialities: Applied Physics

Industries

Semiconductors

Resumes

Resumes

Gianluca Boselli Photo 1

Analog Esd Lab Manager At Texas Instruments

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Position:
Analog ESD Lab Manager at Texas Instruments, Board of Directors at ESD Association
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Work:
Texas Instruments since Sep 2011
Analog ESD Lab Manager
ESD Association since 2009
Board of Directors
Texas Instruments - Dallas, TX Sep 2007 - Aug 2011
Analog ESD Development Manager
Texas Instruments Jan 2001 - Sep 2007
CMOS ESD Technology Development Leader
Education:
Twente University 1997 - 2000
Ph.D., Applied Physics

Publications

Us Patents

Guardwall Structures For Esd Protection

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US Patent:
7145204, Dec 5, 2006
Filed:
Apr 15, 2005
Appl. No.:
11/107033
Inventors:
Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/62
US Classification:
257355, 257356, 257357, 257358, 257359, 257360, 257361, 257363
Abstract:
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well. Further a finger-shaped diode () with its cathode () located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall ().

Pmos Electrostatic Discharge (Esd) Protection Device

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US Patent:
7196887, Mar 27, 2007
Filed:
May 28, 2003
Appl. No.:
10/446369
Inventors:
Gianluca Boselli - Richardson TX, US
Vijay Kumar Reddy - Plano TX, US
Ekanayake Ajith Amerasekera - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

Body-Biased Pmos Protection Against Electrostatic Discharge

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US Patent:
7256460, Aug 14, 2007
Filed:
Nov 30, 2004
Appl. No.:
11/001899
Inventors:
Craig T. Salling - Cupertino CA, US
Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/62
US Classification:
257358, 257360, 257363, 257E29014
Abstract:
A protection circuit for protecting an integrated circuit pad against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor (preferably pMOS) in a substrate (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor (for example about 40 to 60Ω) is connected between the pad and the component and is operable to generate a voltage drop (about 0. 5 to 1. 0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.

Local Esd Protection For Low-Capacitance Applications

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US Patent:
7277263, Oct 2, 2007
Filed:
Sep 8, 2004
Appl. No.:
10/936912
Inventors:
Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad () against ESD events, when the I/O pad is located between a power pad () and a ground potential pad (). A first diode () and a second diode () are connected in series, the anode () of the series connected to the I/O pad and the cathode () connected to the power pad. A third diode () has its anode () tied to the ground pad and its cathode () tied to the I/O pad. A string () of at least one diode has its anode () connected to the series between the first and second diode (node ), isolated from the I/O pad, and its cathode () connected to the ground pad. The string () may comprise three or more diodes.

Guardwall Structures For Esd Protection

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US Patent:
7282767, Oct 16, 2007
Filed:
Jun 17, 2005
Appl. No.:
11/155062
Inventors:
Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/62
US Classification:
257355, 257E51005
Abstract:
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well, which touches source junction. Source has further an ohmic (silicided) connection to contact. A finger-shaped diode () with its cathode () is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall ().

Semiconductor Dual Guardring Arrangement

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US Patent:
7348643, Mar 25, 2008
Filed:
Jun 6, 2006
Appl. No.:
11/447359
Inventors:
Gianluca Boselli - Farmers Branch TX, US
Charvaka Duvvury - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 29/76
US Classification:
257409, 257355, 257362
Abstract:
A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.

Local Esd Protection For Low-Capicitance Applications

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US Patent:
7667243, Feb 23, 2010
Filed:
Apr 25, 2007
Appl. No.:
11/739801
Inventors:
Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/62
US Classification:
257173, 257355, 257360, 257E29219
Abstract:
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad () against ESD events, when the I/O pad is located between a power pad () and a ground potential pad (). A first diode () and a second diode () are connected in series, the anode () of the series connected to the I/O pad and the cathode () connected to the power pad. A third diode () has its anode () tied to the ground pad and its cathode () tied to the I/O pad. A string () of at least one diode has its anode () connected to the series between the first and second diode (node ), isolated from the I/O pad, and its cathode () connected to the ground pad. The string () may comprise three or more diodes.

Low Capacitance Scr With Trigger Element

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US Patent:
7728349, Jun 1, 2010
Filed:
Oct 11, 2005
Appl. No.:
11/247452
Inventors:
Gianluca Boselli - Farmers Branch TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 29/74
US Classification:
257111, 257107, 257E29113
Abstract:
A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.
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Gianluca Boselli from Plano, TX, age ~57 Get Report