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Gene Wei Shen

from San Jose, CA
Age ~60
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Also known as:
Gene W Shen, Gene W Sheen
Phone and address:
6717 Elwood Rd, San Jose, CA 95120
Related to:
James ShapiroJingwei Zhang, 59Hsow Chen, 71
Connected to:
Allan Shen, 32Alvin S Shen, 93Amber Shen, 47Amy Shen, 85Anni Shen, 32Bailey Y Shen, 36Brandon Shen, 44Cary Z Shen, 77Chengyue Shen, 49Chin C Shen, 77

Gene Shen Phones & Addresses

  • 6717 Elwood Rd, San Jose, CA 95120
  • 5972 Aster Dr, San Jose, CA 95123
  • 232 Las Miradas Dr, Los Gatos, CA 95032
  • 181 Central Ave, Mountain View, CA 94043
  • Austin, TX
  • Ithaca, NY
  • Santa Clara, CA

Resumes

Resumes

Gene Shen Photo 1

Manager, Pcie Switch Sw Development

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Location:
2745 Huntington Dr, San Marino, CA 91108
Industry:
Computer Hardware
Work:
Broadcom
Manager, Pcie Switch Sw Development
Virtual Instruments Nov 2012 - Nov 2015
Senior Engineering Manager
Violin Memory Nov 2011 - Sep 2012
Principal Architect
Seamicro Feb 2008 - Nov 2011
Member of Technical Staff
Amd Apr 2001 - Feb 2008
Rtl Manager and Principal Member of Technical Staff
Education:
Massachusetts Institute of Technology
Bachelors, Bachelor of Science, Electrical Engineering Cornell University
Masters, Master of Engineering, Electrical Engineering, Engineering
Skills:
Processors
Vlsi
Asic
Soc
Microprocessors
Computer Architecture
Rtl Design
Fpga
Verilog
Microarchitecture
X86
Eda
Functional Verification
Semiconductors
Systemverilog
Fibre Channel
Integrated Circuit Design
Hardware Architecture
Algorithms
High Performance Computing
Gene Shen Photo 2

Clinic Director

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Work:
Gramercy Physical Therapy
Clinic Director
Gene Shen Photo 3

Gene Shen

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Publications

Us Patents

Microprocessor And Address Translation Method For Microprocessor

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US Patent:
6553477, Apr 22, 2003
Filed:
Nov 6, 2000
Appl. No.:
09/707347
Inventors:
Murali V. Krishna - Campbell CA
Vipul Parikh - Campbell CA
Michael Butler - Campbell CA
Gene Shen - Campbell CA
Masahito Kubo - Kawasaki, JP
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 1200
US Classification:
711207, 711122, 711126, 711128, 711205, 711206, 700200
Abstract:
A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Method And System For Architectural Power Estimation

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US Patent:
7051300, May 23, 2006
Filed:
Sep 4, 2003
Appl. No.:
10/655390
Inventors:
Gene W. Shen - San Jose CA, US
Stephan G. Meier - Sunnyvale CA, US
Leslie A. Barnes - Ben Lomond CA, US
Paul S. Keltcher - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5
Abstract:
A method is provided for architectural integrated circuit power estimation. The method may include receiving a plurality of respective energy events, receiving a plurality of base-level energy models, and generating a plurality of power models. Each power model may hierarchically instantiate one or more of the base-level energy models. The method may further include mapping each respective energy event to one or more of the plurality of power models. The method may further include hierarchically evaluating a particular base-level energy model corresponding to a given respective energy event, estimating an energy associated with evaluation of the particular base-level energy model, and accumulating the energy in a power estimate corresponding to the given respective energy event.

Microtlb And Micro Tag For Reducing Power In A Processor

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US Patent:
7117290, Oct 3, 2006
Filed:
Sep 3, 2003
Appl. No.:
10/653749
Inventors:
Gene W. Shen - San Jose CA, US
S. Craig Nelson - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 12/08
US Classification:
711 3, 711207
Abstract:
A processor comprises a cache, a first TLB, and a tag circuit. The cache comprises a data memory storing a plurality of cache lines and a tag memory storing a plurality of tags. Each of the tags corresponds to a respective one of the cache lines. The first TLB stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB. The tag circuit is configured to identify one or more of the plurality of cache lines that are stored in the cache and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB and a hit by the first virtual address in the tag circuit, the tag circuit is configured to prevent a read of the tag memory in the cache.

Redirect Recovery Cache That Receives Branch Misprediction Redirects And Caches Instructions To Be Dispatched In Response To The Redirects

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US Patent:
7685410, Mar 23, 2010
Filed:
Feb 13, 2007
Appl. No.:
11/674566
Inventors:
Gene W. Shen - San Jose CA, US
Sean Lie - Santa Clara CA, US
Assignee:
Global Foundries Inc. - Grand Cayman
International Classification:
G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00
US Classification:
712237
Abstract:
In one embodiment, a processor comprises a branch resolution unit and a redirect recovery cache. The branch resolution unit is configured to detect a mispredicted branch operation, and to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch operation. The redirect recovery cache comprises a plurality of cache entries, each cache entry configured to store operations corresponding to instructions fetched in response to respective mispredicted branch operations. The redirect recovery cache is coupled to receive the redirect address and, if the redirect address is a hit in the redirect recovery cache, the redirect recovery cache is configured to supply operations from the hit cache entry to a pipeline of the processor, bypassing at least one initial pipeline stage.

Distributed Dispatch With Concurrent, Out-Of-Order Dispatch

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US Patent:
7725690, May 25, 2010
Filed:
Feb 13, 2007
Appl. No.:
11/674562
Inventors:
Gene W. Shen - San Jose CA, US
Sean Lie - Santa Clara CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9/00
US Classification:
712220
Abstract:
In one embodiment, a processor comprises an instruction buffer and a pick unit. The instruction buffer is coupled to receive instructions fetched from an instruction cache. The pick unit is configured to select up to N instructions from the instruction buffer for concurrent transmission to respective slots of a plurality of slots, where N is an integer greater than one. Additionally, the pick unit is configured to transmit an oldest instruction of the selected instructions to any of the plurality of slots even if a number of the selected instructions is greater than one. The pick unit is configured to concurrently transmit other ones of the selected instructions to other slots of the plurality of slots based on the slot to which the oldest instruction is transmitted. Some embodiments comprise a computer system including the processor and a communication device configured to communicate with another computer system.

Multiple-Core Processor With Hierarchical Microcode Store

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US Patent:
7743232, Jun 22, 2010
Filed:
Jul 18, 2007
Appl. No.:
11/779642
Inventors:
Gene W. Shen - San Jose CA, US
Bruce R. Holloway - Boulder Creek CA, US
Sean Lie - Santa Clara CA, US
Michael G. Butler - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9/24
US Classification:
712211
Abstract:
A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.

Processing Pipeline Having Parallel Dispatch And Method Thereof

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US Patent:
7793080, Sep 7, 2010
Filed:
Dec 31, 2007
Appl. No.:
11/967924
Inventors:
Gene Shen - San Jose CA, US
Sean Lie - Santa Clara CA, US
International Classification:
G06F 9/30
US Classification:
712215, 712212
Abstract:
One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e. g. , integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.

Method And Apparatus For Length Decoding Variable Length Instructions

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US Patent:
7818542, Oct 19, 2010
Filed:
Jul 10, 2007
Appl. No.:
11/775451
Inventors:
Gene W. Shen - San Jose CA, US
Sean Lie - Santa Clara CA, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
G06F 9/30
G06F 9/32
US Classification:
712210, 712208, 712212
Abstract:
A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
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Gene Wei Shen from San Jose, CA, age ~60 Get Report