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Geetak Gupta

from Ventura, CA
Age ~36
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Also known as:
Geeta K Gupta
Related to:
Ashish GuptaDeepak Gandhi, 74Anant Gupta, 33Cherry Gupta, 41Mridula M Gupta, 62Sushant K Gupta, 74Raj M Gandhi, 39Saurabh H Gupta, 28Mitan M Gandhi, 72Neil M Gandhi, 42M Gupta, 62Chirag Gupta, 34
Connected to:
Aashish Gupta, 45Abhijat A Gupta, 44Ajaya Gupta, 64Ajaykumar K Gupta, 59Akriti Gupta, 35Akshey Gupta, 47Alankar A Gupta, 84Amartya S Gupta, 45Amitesh K Gupta, 45Amitkumar N Gupta, 44

Geetak Gupta Phones & Addresses

  • Ventura, CA
  • Santa Barbara, CA
  • Fremont, CA

Work

Company: Uc santa barbara Sep 2010 Address: Santa Barbara, California Area Position: Graduate student researcher

Education

Degree: Ph.D. School / High School: University of California, Santa Barbara 2010 to 2015 Specialities: III-Nitride Electronic Devices

Skills

Matlab • Characterization • Latex • Spectroscopy • Afm • C++ • Photonics • Nanotechnology • Microsoft Office • Photolithography • Scanning Electron Microscopy • Semiconductor Device • Programming • Thin Films • Mathematica • Gan Electronics • Semiconductor Fabrication • Originlab • Python • Jmp • Ltspice

Languages

English • Hindi

Ranks

Certificate: Introduction To Power Electronics

Industries

Semiconductors

Resumes

Resumes

Geetak Gupta Photo 1

Member Of Technical Staff, Chief Technology Officer

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Location:
1953 Elise Way, Santa Barbara, CA 93109
Industry:
Semiconductors
Work:
UC Santa Barbara - Santa Barbara, California Area since Sep 2010
Graduate Student Researcher
UC Santa Barbara - Santa Barbara, California Area May 2009 - Jul 2009
Summer Intern
Education:
University of California, Santa Barbara 2010 - 2015
Ph.D., III-Nitride Electronic Devices University of California, Santa Barbara 2010 - 2012
MS, Electrical and Computer Engineering Indian Institute of Technology, Kanpur 2006 - 2010
Bachelor of Technology, Electrical Engineering
Skills:
Matlab
Characterization
Latex
Spectroscopy
Afm
C++
Photonics
Nanotechnology
Microsoft Office
Photolithography
Scanning Electron Microscopy
Semiconductor Device
Programming
Thin Films
Mathematica
Gan Electronics
Semiconductor Fabrication
Originlab
Python
Jmp
Ltspice
Languages:
English
Hindi
Certifications:
Introduction To Power Electronics
Converter Circuits

Publications

Us Patents

Iii-Nitride Devices Including A Graded Depleting Layer

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US Patent:
20200212180, Jul 2, 2020
Filed:
Mar 9, 2020
Appl. No.:
16/813577
Inventors:
- Goleta CA, US
Rakesh K. Lal - Isla Vista CA, US
Geetak Gupta - Goleta CA, US
Carl Joseph Neufeld - Goleta CA, US
David Rhodes - Santa Barbara CA, US
International Classification:
H01L 29/06
H01L 29/417
H01L 29/423
H01L 29/66
H01L 29/778
H01L 29/872
H01L 29/20
H01L 29/205
H01L 29/40
Abstract:
A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

Lateral Iii-Nitride Devices Including A Vertical Gate Module

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US Patent:
20200119179, Apr 16, 2020
Filed:
Oct 10, 2019
Appl. No.:
16/598510
Inventors:
- Goleta CA, US
Davide Bisi - Goleta CA, US
Geetak Gupta - Goleta CA, US
Carl Joseph Neufeld - Goleta CA, US
Brian L. Swenson - Santa Barbara CA, US
Rakesh K. Lal - Isla Vista CA, US
International Classification:
H01L 29/778
H01L 29/205
H01L 29/10
H01L 29/06
H01L 29/66
Abstract:
A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

Iii-Nitride Devices Including A Graded Depleting Layer

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US Patent:
20190198615, Jun 27, 2019
Filed:
Feb 27, 2019
Appl. No.:
16/287211
Inventors:
- Goleta CA, US
Rakesh K. Lal - Isla Vista CA, US
Geetak Gupta - Goleta CA, US
Carl Joseph Neufeld - Goleta CA, US
David Rhodes - Santa Barbara CA, US
International Classification:
H01L 29/06
H01L 29/205
H01L 29/20
H01L 29/778
H01L 29/40
H01L 29/872
H01L 29/66
H01L 29/423
H01L 29/417
Abstract:
A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

Iii-Nitride Devices Including A Graded Depleting Layer

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US Patent:
20180158909, Jun 7, 2018
Filed:
May 31, 2017
Appl. No.:
15/564498
Inventors:
- Goleta CA, US
Rakesh K. Lal - Isla Vista CA, US
Geetak Gupta - Goleta CA, US
Carl Joseph Neufeld - Goleta CA, US
David Rhodes - Goleta CA, US
International Classification:
H01L 29/06
H01L 29/205
H01L 29/20
H01L 29/40
H01L 29/423
H01L 29/778
H01L 29/66
H01L 29/872
H01L 23/495
Abstract:
A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.
Control profile
Geetak Gupta from Ventura, CA, age ~36 Get Report