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Gary C Hsueh

from San Francisco, CA
Age ~48
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Also known as:
Gary Changhao Hsueh, Gary C Sueh
Phone and address:
57 Capra Way, San Francisco, CA 94123
Related to:
Peter T Tung, 60David C Chung, 49
Connected to:
Aileen Hsueh, 63Angela J Hsueh, 44Austin K Hsueh, 36Claudia L Hsueh, 54Gregory K Hsueh, 66Liang Hsueh, 103Lin Hsueh, 70Linda H Hsueh, 74Michael C Hsueh, 50Ping W Hsueh, 67

Gary Hsueh Phones & Addresses

  • 57 Capra Way, San Francisco, CA 94123
  • South Lake Tahoe, CA
  • 944 Cape Jessup Dr, San Jose, CA 95133 (408) 251-9019
  • Los Angeles, CA
  • San Luis Obispo, CA
  • San Diego, CA
  • Newport Beach, CA
  • El Dorado, CA

Work

Position: Medical Professional

Education

Degree: Graduate or professional degree

Emails

m***h@email.msn.com

Resumes

Resumes

Gary Hsueh Photo 1

Director Of Mobility Programs

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Location:
San Francisco, CA
Industry:
Transportation/Trucking/Railroad
Work:
Prospect Silicon Valley
Director of Mobility Programs
Arup Feb 1, 2004 - Sep 2017
Senior Transportation Planner
City of Benicia Mar 2003 - Aug 2004
Planning Assistant
City of Pittsburg Oct 2001 - Feb 2003
Planning Intern
Chs Consulting Group Oct 2001 - Feb 2003
Director of Mobility Programs
Education:
San Jose State University 2008 - 2012
Master of Science, Masters, Management University of California, Berkeley 1994 - 2000
Bachelors, Bachelor of Arts, Geography
Skills:
Transportation Planning
Land Use Planning
Transit Oriented Development
Comprehensive Planning
Public Transport
Project Management
Feasibility Studies
Analysis of Transportation Technology
Interests:
Environment
Certifications:
Aicp
Gary Hsueh Photo 2

Co-Founder And Managing Partner

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Location:
San Francisco, CA
Industry:
Financial Services
Work:
Catapult Capital
Co-Founder and Managing Partner
Dragonfly Partners
Senior Advisor
Yahoo Jun 2014 - Oct 2016
Vp, Global Head of Search Partnerships
Endue Oct 2011 - Feb 2014
Co-Founder and Chief Executive Officer
Goldman Sachs Jul 2006 - Oct 2011
Vice President, Technology and Media Investment Banking
Education:
Ucla Anderson School of Management
Master of Business Administration, Masters, Finance California Polytechnic State University - San Luis Obispo
Bachelors, Bachelor of Science, Industrial Engineering
Skills:
Strategy
Financial Modeling
Investment Banking
Mergers and Acquisitions
Financial Analysis
Start Ups
Business Strategy
Ipo
Corporate Finance
Venture Capital
New Business Development
Equities
Cross Functional Team Leadership
Valuation
Analysis
Private Equity
Business Development
Financial Structuring
Management
Internet
Manufacturing Operations
Strategic Analysis
Gary Hsueh Photo 3

Gary Hsueh

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Location:
San Francisco Bay Area
Industry:
Semiconductors
Certifications:
CFA, CFA Institute
Gary Hsueh Photo 4

Associate At Goldman Sachs

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Location:
San Francisco Bay Area
Industry:
Investment Banking

Business Records

Name / Title
Company / Classification
Phones & Addresses
Gary Hsueh
Marina Cloth LLC
Children's Clothing · Marina Operation · Marinas, Nsk
1728 Un St, San Francisco, CA 94123
57 Capra Way, San Francisco, CA 94123

Publications

Us Patents

Method For Etching Low K Dielectrics

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US Patent:
6547977, Apr 15, 2003
Filed:
Jul 5, 2000
Appl. No.:
09/610915
Inventors:
Chun Yan - Santa Clara CA
Gary C. Hsueh - San Jose CA
Yan Ye - Campbell CA
Diana Xiaobing Ma - Saratoga CA
Assignee:
Applied Materials Inc. - Santa Clara CA
International Classification:
C03C 1500
US Classification:
216 72, 216 67, 216 74, 216 79, 216 81, 438735, 438743
Abstract:
The present disclosure pertains to a method for plasma etching of low k materials, particularly polymeric-based low k materials. Preferably the polymeric-based materials are organic-based materials. The method employs an etchant plasma where the major etchant species are generated from a halogen other than fluorine and oxygen. The preferred halogen is chlorine. The volumetric (flow rate) ratio of the halogen:oxygen in the plasma source gas ranges from about 1:20 to about 20:1. The atomic ratio of the halogen:oxygen preferably falls within the range from about 1:20 to about 20:1. When the halogen is chlorine, the preferred atomic ratio of chlorine:oxygen ranges from about 1:10 to about 5:1. When this atomic ratio of chlorine:oxygen is used, the etch selectivity for the low k material over adjacent oxygen-comprising or nitrogen-comprising layers is advantageous, typically in excess of about 10:1. The plasma source gas may contain additives in an amount of 15% or less by volume which are designed to improve selectivity for the low k dielectric over an adjacent material, to provide a better etch profile, or to provide better critical dimension control, for example. When the additive contains fluorine, the amount of the additive is such that residual chlorine on the etched surface of the low k material comprises less than 5 atomic %.

Method And Apparatus Employing Integrated Metrology For Improved Dielectric Etch Efficiency

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US Patent:
7265382, Sep 4, 2007
Filed:
Nov 12, 2002
Appl. No.:
10/293595
Inventors:
Dimitris Lymberopoulos - San Jose CA, US
Gary Hsueh - San Francisco CA, US
Sukesh Mohan - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 23/58
H01L 21/66
G01N 23/00
US Classification:
257 48, 257E21521, 257E21529, 438 14, 250310, 25049223, 250492
Abstract:
A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e. g. , the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.

Integrated System For Oxide Etching And Metal Liner Deposition

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US Patent:
20030027427, Feb 6, 2003
Filed:
Aug 6, 2001
Appl. No.:
09/922980
Inventors:
Diana Ma - Saratoga CA, US
Sy Shieh - Palo Alto CA, US
Yan Ye - Saratoga CA, US
Tetsuya Ishikawa - Saratoga CA, US
Gary Hsueh - Cupertino CA, US
Assignee:
Applied Materials, Inc.
International Classification:
H01L021/311
C23C016/00
US Classification:
438/700000, 118/719000
Abstract:
An integrated process and system for etching a hole in an oxide layer and conformally coating a liner for metal filling. The wafer with a patterned photoresist mask is loaded into a first transfer chamber held at a vacuum of less than 1 Torr. An oxide etch reactor etches the oxide down to a nitride etch stop and barrier layer to form a hole through the oxide. Thereafter, the photoresist is ashed, and the barrier layer is removed. The wafer is transferred through a gated vacuum passageway to a second transfer chamber held at a vacuum no more than 10Torr. In at least two PVD or CVD deposition chambers connected to the second transfer chamber, a barrier layer of Ta/TaN is coated onto sides of the hole and a copper seed layer is deposited over the barrier layer. The invention may be limited to the operations subsequent to ashing.

Backside Gas Quick Dump Apparatus For A Semiconductor Wafer Processing System

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US Patent:
58569065, Jan 5, 1999
Filed:
May 12, 1997
Appl. No.:
8/854509
Inventors:
Arnold Kholodenko - San Francisco CA
Maya Shendon - San Carlos CA
Gary Hsueh - Berkeley CA
James E. Sammons - Santa Clara CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H02N 1300
US Classification:
361234
Abstract:
Apparatus for retaining a workpiece in a semiconductor wafer processing system. The apparatus has a collector positioned between an electrostatic chuck pedestal and the floor of the processing chamber. The collector has inlet and exhaust control valves connected to inlet and exhaust ports for providing and expelling a backside heat transfer gas (e. g. , Helium). Heat transfer exhaust cavities in the collector are connected to the exhaust port to rapidly draw the gas off the backside of the wafer. Additionally, control of the heat transfer gas layer uniformity during processing is achieved by opening and closing the valves to the inlet and exhaust ports as required.
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Gary C Hsueh from San Francisco, CA, age ~48 Get Report