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Frank Chris Hui

from Wildwood, MO
Age ~64
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Related to:
Aigoon L Leong, 92Goon Leong LaiKyle E Johnson, 64Hoi K Yee, 62Kenneth E Johnson, 57Kwok Sun HuiWayne Tung, 63David F Johnson, 57Kay E Hui, 59Leon Johnson, 54Thomas Hui, 66Holly A Gagnon, 72Dolores F Johnson, 95Yu S Tung, 90Loretta F Hui, 63K C YeeRhonda M Griffin, 63Bill D Johnson
Connected to:
Aaron K Hui, 37Alyson L Hui, 62Ana L Hui, 65Bill C Hui, 48Bruce M Hui, 40Charlie J Hui, 66Che Hui, 38Christa S Hui, 54Christopher J Hui, 39Chui H Hui, 63

Frank Hui Phones & Addresses

  • 1347 Wellington View Pl, Chesterfield, MO 63005 (636) 273-9988
  • Wildwood, MO
  • Irvine, CA
  • 2555 Thompson Ave, Tustin, CA 92782
  • Anchorage, AK
  • Federal Way, WA
  • Orange, CA
  • Shoreline, WA
  • Flushing, NY

Resumes

Resumes

Frank Hui Photo 1

Administrative Manager, Vice President

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Location:
1640 Van Ness Ave, San Francisco, CA 94109
Industry:
Financial Services
Work:
Bank of America
Administrative Manager, Vice President
Morgan Stanley Jun 2009 - Oct 2012
Complex Risk Officer, Assistant Vice President
Morgan Stanley Mar 2005 - Jun 2009
Operations Manager, Complex Administrative Manager , Assistant Vice President
A.g. Edwards 2005 - 2005
Branch Examiner
Merrill Lynch 2001 - 2004
Complex Field Service Manager
Skills:
Series 7
Finra
Wealth Management
Financial Services
Series 63
Risk Management
Securities
Equities
Operations Management
Options
Uniform Combined State Law
Mutual Funds
Retirement Planning
Portfolio Management
Complaince
Training
Change Management
Investment Advisory
Asset Allocation
Fixed Income
Investments
Financial Risk
Relationship Management
Finance
Wealth Management Services
Alternative Investments
Asset Management
Investment Strategies
Series 9
Series 10
Series 66
Expense Management
Bonds
Legal Compliance
Trading
Etfs
Financial Advisory
Wealth
Retirement
Investment Management
Management
Leadership
Customer Service
Service Management
Hr Policies
Project Coordination
Interests:
Animal Welfare
Children
Frank Hui Photo 2

Frank Hui

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Frank Hui Photo 3

Frank Hui

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Frank Hui Photo 4

Frank Hui

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Frank C. Hui
HUI FAMILY LIMITED PARTNERSHIP

Publications

Us Patents

Method For Fabricating A Flash Memory Cell Utilizing A High-K Metal Gate Process And Related Structure

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US Patent:
8558300, Oct 15, 2013
Filed:
Nov 6, 2009
Appl. No.:
12/590370
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Frank Hui - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/788
US Classification:
257316, 257412
Abstract:
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Semiconductor Device With Semiconductor Fins And Floating Gate

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US Patent:
20130285135, Oct 31, 2013
Filed:
Apr 30, 2012
Appl. No.:
13/460336
Inventors:
Frank Hui - Irvine CA, US
Neal Kistler - Laguna Niguel CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01L 29/788
US Classification:
257316, 257E293
Abstract:
According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

Dual Anti-Fuse

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US Patent:
20140015095, Jan 16, 2014
Filed:
Jul 12, 2012
Appl. No.:
13/548123
Inventors:
Frank Hui - Irvine CA, US
Neal Kistler - Laguna Niguel CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01L 23/525
US Classification:
257530, 257E23147
Abstract:
According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

Flash Memory Utilizing A High-K Metal Gate

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US Patent:
20140038404, Feb 6, 2014
Filed:
Oct 10, 2013
Appl. No.:
14/050748
Inventors:
Xiangdong Chen - Irvine CA, US
Frank Hui - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 21/28
US Classification:
438593
Abstract:
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Semiconductor Device With A Vertical Channel Formed Through A Plurality Of Semiconductor Layers

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US Patent:
20160308042, Oct 20, 2016
Filed:
Jun 27, 2016
Appl. No.:
15/193718
Inventors:
- Irvine CA, US
Frank Hui - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/78
H01L 29/66
H01L 29/10
Abstract:
Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Semiconductor Device With A Vertical Channel

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US Patent:
20160005850, Jan 7, 2016
Filed:
Oct 31, 2014
Appl. No.:
14/529959
Inventors:
- Irvine CA, US
Frank Hui - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/78
H01L 29/10
Abstract:
Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.
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Frank Chris Hui from Wildwood, MO, age ~64 Get Report