Francisco G Cano

6363516, Mar 26, 2002

Nov 12, 1999

09/438808

Francisco A. Cano - Missouri City TX
Nagaraj N. Savithri - Dallas TX
Vijaya Gunturi - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1750

716 5, 716 13, 716 10

In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines. Each cutout portion of the over the cell routing (OCR) is combined with the respective cell instance and OCR parasitic data is extracted with reference to the respective cell. For each cell instance, the intracellular parasitic data derived once for the cell is combined with the OCR parasitic information derived for that cell instance in order to form a coupled simulation model.

6381704, Apr 30, 2002

Jan 29, 1999

09/240271

Francisco A. Cano - Missouri City TX
Rajib Nag - Missouri City TX
Robert E. Farrell - Murphy TX

Texas Instruments Incorporated - Dallas TX

G06F 104

713600, 713400, 713500, 710 58, 714731

A clock generation circuit with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry in or out of the non-overlap feedback path on signal line. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit or a scan latch also can select the non-overlap time period.

6581201, Jun 17, 2003

Oct 2, 2001

09/969378

Francisco A. Cano - Missouri City TX
David A. Thomas - Missouri City TX
Clive Bittlestone - Los Gatos CA

Texas Instruments Incorporated - Dallas TX

G06F 1750

716 12, 716 13

An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level M a second set of power buses and on interconnect level M and a third set of power buses and on interconnect level M The set of power buses on level M are oriented in the same direction as the set of power buses on level M and both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M -M power vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M -M power vias. Dummy cell with M -M power vias is positioned as needed so as not to exceed a maximum strapping distance D A maximum value for distance D is selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.

7365556, Apr 29, 2008

Sep 2, 2005

11/218650

Francisco Cano - Missouri City TX, US
Juan C. Martinez - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G01R 31/26

324765

An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

7382147, Jun 3, 2008

Mar 9, 2007

11/684053

Francisco Cano - Missouri City TX, US
Juan C. Martinez - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G01R 31/26

324765

An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

7446552, Nov 4, 2008

Mar 9, 2007

11/684045

Francisco Cano - Missouri City TX, US
Juan C. Martinez - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G01R 31/26

324765

An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

7446553, Nov 4, 2008

Aug 21, 2007

11/842205

Francisco Cano - Missouri City TX, US
Juan C. Martinez - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G01R 31/02

324765

An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

8144533, Mar 27, 2012

Apr 16, 2010

12/762297

Francisco A. Cano - Sugar Land TX, US

Texas Instruments Incorporated - Dallas TX

G11C 7/00

365194, 36523006, 3652331

A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.