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Farookh J Moogat

from Fremont, CA
Age ~58
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Also known as:
Moogat Farookh, Farook Mooga, A L
Phone and address:
4800 Kentfield Cmn, Fremont, CA 94555
(510) 468-1372
Related to:
Yazdaan F Moogat, 30Jasmine Moogat, 30Aarian MoogatFarzeen F Moogat, 50
Connected to:
Jeffery J Moohr, 132Chan Mooi, 73Siew H Mooi, 51Kelly A Mooij, 46Remko Mooij, 55Alex A Mook, 56Brett L Mook, 52Bryant M Mook, 71Edwin T Mook, 91Joshua A Mook, 37

Farookh Moogat Phones & Addresses

  • 4800 Kentfield Cmn, Fremont, CA 94555 (510) 468-1372
  • San Francisco, CA
  • Fairborn, OH
  • Alameda, CA
  • 4800 Kentfield Cmn, Fremont, CA 94555

Work

Company: Sandisk Jan 2009 Position: Director, nand memory design

Education

Degree: Master of Science, Masters School / High School: Wright State University 1991 to 1994 Specialities: Electrical Engineering

Languages

English

Interests

Exercise • Electronics • Sweepstakes • Nascar • Investing • Reading • Sports • Collecting

Industries

Semiconductors

Resumes

Resumes

Farookh Moogat Photo 1

Director, Nand Memory Design

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Location:
4800 Kentfield Cmn, Fremont, CA 94555
Industry:
Semiconductors
Work:
Sandisk
Director, Nand Memory Design
Wsi Jul 1994 - May 2000
Senior Design Engineer
Sandisk Jul 1994 - May 2000
Senior Manager Nand Memory Design
Waferscale Integration 1994 - 2000
Senior Design Engineer
Thermax 1987 - 1991
Design Engineer
Education:
Wright State University 1991 - 1994
Master of Science, Masters, Electrical Engineering Lmk College of Agriculture, Kadegaon 1984 - 1988
Bachelors, Bachelor of Science, Electronics St. Vincents High School 1970 - 1982
Interests:
Exercise
Electronics
Sweepstakes
Nascar
Investing
Reading
Sports
Collecting
Languages:
English

Publications

Us Patents

Non-Volatile Memory With Redundancy Data Buffered In Data Latches For Defective Locations

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US Patent:
7224605, May 29, 2007
Filed:
Mar 24, 2006
Appl. No.:
11/388408
Inventors:
Farookh Moogat - Fremont CA, US
Shouchang Tsao - San Jose CA, US
Tai-Yuan Tseng - Milpitas CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 16/06
G11C 7/00
US Classification:
36518509, 365200
Abstract:
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

Partition Of Non-Volatile Memory Array To Reduce Bit Line Capacitance

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US Patent:
7313023, Dec 25, 2007
Filed:
Mar 11, 2005
Appl. No.:
11/078173
Inventors:
Yan Li - Milpitas CA, US
Farookh Moogat - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 7/18
G11C 8/12
G11C 7/02
US Classification:
36518513, 36523003, 365207
Abstract:
The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

High-Performance Flash Memory Data Transfer

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US Patent:
7345926, Mar 18, 2008
Filed:
Apr 24, 2006
Appl. No.:
11/379910
Inventors:
Yishai Kagan - Sunnyvale CA, US
Rizwan Ahmed - San Jose CA, US
Farookh Moogat - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
36518533, 36518511
Abstract:
A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Method Of High-Performance Flash Memory Data Transfer

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US Patent:
7366028, Apr 29, 2008
Filed:
Apr 24, 2006
Appl. No.:
11/379895
Inventors:
Yishai Kagan - Sunnyvale CA, US
Rizwan Ahmed - San Jose CA, US
Farookh Moogat - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
36518533, 36518511
Abstract:
A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Method For Column Redundancy Using Data Latches In Solid-State Memories

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US Patent:
7394690, Jul 1, 2008
Filed:
Mar 24, 2006
Appl. No.:
11/389655
Inventors:
Farookh Moogat - Fremont CA, US
Shouchang Tsao - San Jose CA, US
Tai-Yuan Tseng - Milpitas CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 16/06
US Classification:
36518509, 36518905, 365200
Abstract:
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

Systems Utilizing Variable Program Voltage Increment Values In Non-Volatile Memory Program Operations

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US Patent:
7450426, Nov 11, 2008
Filed:
Oct 10, 2006
Appl. No.:
11/548267
Inventors:
Yan Li - Milpitas CA, US
Fanglin Zhang - San Jose CA, US
Toru Miwa - Yokohama, JP
Farookh Moogat - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
36518519, 36518517
Abstract:
The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

Variable Program Voltage Increment Values In Non-Volatile Memory Program Operations

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US Patent:
7474561, Jan 6, 2009
Filed:
Oct 10, 2006
Appl. No.:
11/548264
Inventors:
Yan Li - Milpitas CA, US
Fanglin Zhang - San Jose CA, US
Toru Miwa - Yokohama, JP
Farookh Moogat - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
36518517, 36518519
Abstract:
The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

Method Of Nand Flash Memory Cell Array With Adaptive Memory State Partitioning

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US Patent:
7489547, Feb 10, 2009
Filed:
Dec 29, 2006
Appl. No.:
11/618482
Inventors:
Farookh Moogat - Fremont CA, US
Teruhiko Kamei - Yokohama, JP
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518517, 36518518, 36518503
Abstract:
A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.
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Farookh J Moogat from Fremont, CA, age ~58 Get Report