Fariborz Assaderaghi

6344671, Feb 5, 2002

Dec 14, 1999

09/460885

Jack A. Mandelman - Stormville NY
Fariborz Assaderaghi - Mahopac NY
Michael J. Hargrove - Clinton Corners NY
Peter Smeys - White Plains NY
Norman J. Rohrer - Underhill VT

International Business Machines Corporation - Armonk NY

H01L 27108

257296, 257347, 257901, 257908

A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions.

6352882, Mar 5, 2002

Jul 25, 2000

09/624834

Fariborz Assaderaghi - Mahopac NY
Louis Lu-Chen Hsu - Fishkill NY
Jack Allan Mandelman - Stormville NY

International Business Machines Corporation - Armonk NY

H01L 2100

438155, 438156

Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating positive and negative ESD stresses. In addition, the polysilicon plugs provide a thermal dissipation pathway for directing heat away from the circuitry, and provide a diode for the structure.

6404686, Jun 11, 2002

Jan 26, 2001

09/770912

Anthony Gus Aipperspach - Rochester MN
Fariborz Assaderaghi - Mahopac NY
Todd Alan Christensen - Rochester MN
Douglas Michael Dewanz - Rochester MN
Jente Benedict Kuang - Lakeville MN

International Business Machines Corporation - Armonk NY

G11C 700

365205, 365203, 365207

A high performance, low cell stress, low-power silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary bit and data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. The reduced bit and data line precharge voltage substantially reduces voltage stress applied to the access transistors in the RAM cells. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the. sense amplifier is set. The pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) field effect transistor (FET) in the sense amplifier.

6410369, Jun 25, 2002

Jun 12, 2000

09/591511

Roy Childs Flaker - late of Essex Junction VT
Louis L. Hsu - Fishkill NY
Fariborz Assaderaghi - Mahopac NY
Jack A. Mandelman - Stormville NY

International Business Machines Corporation - Armonk NY

H01L 2100

438149, 438238

A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

6424011, Jul 23, 2002

Aug 31, 1999

09/387059

Fariborz Assaderaghi - Mahopac NY
Louis Lu-Chen Hsu - Fishkill NY
Jack A. Mandelman - Stormville NY

International Business Machines Corporation - Armonk NY

H01L 2701

257350, 438258, 438155

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one semiconductor on insulator substrate and processes for forming a new NVRAM cell structure. Preferably, the semiconductor-on-insulator substrate is an SOI substrate, a silicon on glass substrate or a silicon on sapphire substrate, as appropriate for a particular application.

6429084, Aug 6, 2002

Jun 20, 2001

09/885828

Heemyong Park - LaGrangeville NY
Fariborz Assaderaghi - San Diego CA
Dominic J. Schepis - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 21336

438305, 438300, 438424, 438479, 438589

In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.

6432754, Aug 13, 2002

Feb 20, 2001

09/788979

Fariborz Assaderaghi - Mahopac NY
Tze-Chiang Chen - Yorktown Heights NY
K. Paul Muller - Wappingers Falls NY
Edward Joseph Nowak - Essex Junction VT
Devendra Kumar Sadana - Pleasantville NY
Ghavam G. Shahidi - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

H01L 2100

438149, 257347

The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

6433587, Aug 13, 2002

Mar 17, 2000

09/528207

Fariborz Assaderaghi - Mahopac NY
Kerry Bernstein - Underhill NY
Michael J. Hargrove - Clinton Corners NY
Norman J. Rohrer - Underhill VT
Peter Smeys - White Plaines NY

International Business Machines Corporation - Armonk NY

H03K 19096

326 95, 326 98

A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.