Fabrice C Paillet

6828857, Dec 7, 2004

Dec 11, 2002

10/317763

Fabrice Paillet - Hillsboro OR
Tanay Karnik - Portland OR

Intel Corporation - Santa Clara CA

H03F 318

330264, 330308, 330271

A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a nMOSFET, where their gates are connected together and to the output port of the second stage, and comprises a feedback pMOSFET or resistor to provide negative feedback from the drains of the pMOSFET and nMOSFET to the output port of the second stage.

6903984, Jun 7, 2005

Dec 31, 2003

10/748222

Stephen Tang - Pleasanton CA, US
Ali Keshavarzi - Portland OR, US
Dinesh Somasekhar - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Muhammad Khellah - Lake Oswego OR, US
Yibin Ye - Portland OR, US
Vivek De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C007/00

36518909, 365149, 36518901

A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.

6906973, Jun 14, 2005

Dec 24, 2003

10/746148

Dinesh Somasekhar - Hillsboro OR, US
Yibin Ye - Portland OR, US
Muhammad M. Khellah - Lake Oswego OR, US
Fabrice Paillet - Hillsboro OR, US
Stephen H. Tang - Pleasanton CA, US
Ali Keshavarzi - Portland OR, US
Shih-Lien L. Lu - Portland OR, US
Vivek K. De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C007/00

365203, 365210

Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

6952376, Oct 4, 2005

Dec 22, 2003

10/740551

Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Muhammad M. Khellah - Tigard OR, US
Fabrice Paillet - Hillsboro OR, US
Stephen H. Tang - Pleasanton CA, US
Ali Keshavarzi - Portland OR, US
Shih-Lien Lu - Portland OR, US
Vivek K. De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C007/02

365210, 365203, 365207, 365196

An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

6958640, Oct 25, 2005

Dec 31, 2003

10/748300

KyeHyung Lee - Corvallis OR, US
Jianping Xu - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Tanay Karnik - Portland OR, US

Intel Corporation - Santa Clara CA

H03H011/26

327261, 327280

An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.

6967515, Nov 22, 2005

Mar 24, 2004

10/808785

Fabrice Paillet - Hillsboro OR, US
David Rennie - Etobicoke, CA
Tanay Karnik - Portland OR, US
Jianping Xu - Portland OR, US

Intel Corporation - Santa Clara CA

G06F001/04
H03F003/04

327175, 327132, 327274, 330 9, 330301, 330253

A circuit to provide a differential signal output in response to a single-ended signal input, the circuit allowing for a wide common-mode input signal by providing complementary amplifier structures.

6992339, Jan 31, 2006

Dec 31, 2003

10/750572

Ali Keshavarzi - Portland OR, US
Stephen H. Tang - Beaverton OR, US
Dinesh Somasekhar - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Muhammad M. Khellah - Lake Oswego OR, US
Yibin Ye - Portland OR, US
Shih-Lien L. Lu - Portland OR, US
Vivek K. De - Beaverton OR, US

Intel Corporation - Santa Clara CA

H01L 27/10

257202, 257335

Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

6995605, Feb 7, 2006

Mar 31, 2004

10/813169

Peter Hazucha - Beaverton OR, US
Jianping Xu - Portland OR, US
Gerhard Schrom - Hillsboro OR, US
Tanay Karnik - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Vivek K. De - Beaverton OR, US

Intel Corporation - Santa Clara CA

H03K 5/00

327551, 327311, 327557, 307127

A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.