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Ewald J Detjens

from Berkeley, CA
Age ~73

Ewald Detjens Phones & Addresses

  • 1421 Campus Dr, Berkeley, CA 94708 (415) 517-3381
  • Reno, NV
  • Glen Ellen, CA
  • Santa Rosa, CA
  • 15 Buena Vista Ave, San Francisco, CA 94117
  • 715 Buena Vista Ave, San Francisco, CA 94117
  • Sacramento, CA
  • Oakland, CA

Work

Company: New startup 2006 Position: Entrepreneur

Education

School / High School: UC Berkeley

Skills

Entrepreneurship • Management • Start Ups • Semiconductors • Finance • Business Development • Product Management • Energy • Quantitative Finance • Consulting • Strategy • Business Strategy • Venture Capital • Electrical Engineering • Numerical Analysis • Product Development • Mergers and Acquisitions • Strategic Partnerships • Product Marketing • Embedded Systems • Machine Learning

Industries

Financial Services

Resumes

Resumes

Ewald Detjens Photo 1

Head Of Knowledge Engineering

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Location:
Berkeley, CA
Industry:
Financial Services
Work:
new startup since 2006
entrepreneur

Circuit Semantics Inc. 2003 - 2006
CEO

Bridges2silicon, 2001 - 2002
CEO

Mentor Graphics 1995 - 1997
Chief Scientist

Exemplar Logic 1987 - 1995
founder and CEO
Education:
UC Berkeley
Skills:
Entrepreneurship
Management
Start Ups
Semiconductors
Finance
Business Development
Product Management
Energy
Quantitative Finance
Consulting
Strategy
Business Strategy
Venture Capital
Electrical Engineering
Numerical Analysis
Product Development
Mergers and Acquisitions
Strategic Partnerships
Product Marketing
Embedded Systems
Machine Learning

Publications

Us Patents

Hardware-Based Hdl Code Coverage And Design Analysis

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US Patent:
7836416, Nov 16, 2010
Filed:
Apr 13, 2007
Appl. No.:
11/786865
Inventors:
Nils Endric Schubert - Neu-Ulm, DE
John Mark Beardslee - Menlo Park CA, US
Gernot Heinrich Koch - Waghaeusel, DE
Ewald John Detjens - San Francisco CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 4, 716 6, 716 18, 703 13, 703 14
Abstract:
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.

Hardware-Based Hdl Code Coverage And Design Analysis

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US Patent:
20040025122, Feb 5, 2004
Filed:
Feb 28, 2003
Appl. No.:
10/377907
Inventors:
Nils Schubert - Neu-Ulm, DE
John Beardslee - Menlo Park CA, US
Gernot Koch - Waghaeusel, DE
Ewald Detjens - San Francisco CA, US
International Classification:
G06F017/50
US Classification:
716/004000, 716/012000, 716/008000, 716/017000, 716/005000
Abstract:
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.
Ewald J Detjens from Berkeley, CA, age ~73 Get Report