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Evan M Fledell

from Portland, OR
Age ~45
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Also known as:
Evan Marc Fledell, Evan M Flendell, Marc E Fledell
Related to:
Katherine E Wishart, 35James Thompson, 53Carley N Thompson, 45Barbara G Fledell, 73Charley N ThompsonHeather L Thompson, 44John E Thompson, 49Sandra L Anglemoyer, 74Norman D Fledell, 75Aaron B Fledell, 51
Connected to:
Barbara P Flederbach, 79Gary R Fleder, 62John R Fleder, 78Kelly A Flederbach, 62Mark F Flederbach, 71Casondra J Fleece, 37Jack A Fleece, 72Morgan Fleece, 34Michael S Fleecs, 61Suzanna Fleegal, 42

Evan Fledell Phones & Addresses

  • Portland, OR
  • 7792 Laird Pl, Aloha, OR 97007 (503) 848-7270 (503) 848-7639 (503) 690-8907
  • 2138 NW Thorncroft Dr, Hillsboro, OR 97124 (503) 690-8907
  • Beaverton, OR
  • 17877 NW 177Th Ave, Alachua, FL 32615 (352) 339-6952
  • Gainesville, FL
  • Miami, FL
  • 17877 NW 177Th Ave, Alachua, FL 32615 (386) 418-8869

Work

Company: Intel corporation Mar 2019 Position: Senior staff test r and d electrical engineer

Education

Degree: Bachelor's degree or higher

Skills

Signal Integrity • Semiconductors • Intel • Eda • Testing • Ic • Soc • Mixed Signal • Analog • Asic • Engineering • Debugging • Characterization • Hardware Architecture • R&D • Cmos • Semiconductor Industry • Circuit Design • Dft • Failure Analysis • Integrated Circuits • Research and Development

Industries

Semiconductors

Resumes

Resumes

Evan Fledell Photo 1

Senior Staff Test R And D Electrical Engineer

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Senior Staff Test R and D Electrical Engineer
Skills:
Signal Integrity
Semiconductors
Intel
Eda
Testing
Ic
Soc
Mixed Signal
Analog
Asic
Engineering
Debugging
Characterization
Hardware Architecture
R&D
Cmos
Semiconductor Industry
Circuit Design
Dft
Failure Analysis
Integrated Circuits
Research and Development

Publications

Us Patents

Interposer To Regulate Current For Wafer Test Tooling

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US Patent:
20140029150, Jan 30, 2014
Filed:
Mar 6, 2012
Appl. No.:
13/976970
Inventors:
Evan M. Fledell - Beaverton OR, US
Paul B. Fischer - Portland OR, US
Roy E. Swart - Hillsboro OR, US
Timothy J. Maloney - Palo Alto CA, US
Jack D. Pippin - Portland OR, US
International Classification:
H02H 9/02
US Classification:
361 939
Abstract:
An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.

Converged Test Platforms And Processes For Class And System Testing Of Integrated Circuits

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US Patent:
20180252772, Sep 6, 2018
Filed:
Mar 1, 2017
Appl. No.:
15/447095
Inventors:
- Santa Clara CA, US
Evan M. Fledell - Hillsboro OR, US
Mustapha A. Abdulai - Hillsboro OR, US
John M. Peterson - Hillsboro OR, US
Dinia P. Kitendaugh - Beaverton OR, US
Pooya Tadayon - Portland OR, US
Jin Pan - Portland OR, US
David Shia - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/3185
G01R 31/28
Abstract:
A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

Device, System And Method For Providing Zone-Based Configuration Of Socket Structures

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US Patent:
20170187133, Jun 29, 2017
Filed:
Dec 23, 2015
Appl. No.:
14/757972
Inventors:
- Santa Clara CA, US
Zhen ZHOU - Tucson AZ, US
Evan M. FLEDELL - BEAVERTON OR, US
International Classification:
H01R 12/70
H05K 3/30
Abstract:
Techniques and mechanisms for providing socket connection to a substrate. In an embodiment, a socket device includes a first socket body portion that is to provide for signal exchanges as part of a socket connector including the first socket body portion and a second socket body portion. The first socket body portion and the second socket body portion comprise respective zones, wherein, of the two zones, only one such zone has a first electro-mechanical characteristic. The first electro-mechanical characteristic is selected from the group consisting of an interconnect dimension, an interconnect material, an interconnect structure, a socket body material, and a shielding structure. In another embodiment, modular socket sub-assemblies each comprise a respective one of the first zone and the second zone.

Mechanism For Facilitating A Dynamic Electro-Mechanical Interconnect Having A Cavity For Embedding Electrical Components And Isolating Electrical Paths

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US Patent:
20140091824, Apr 3, 2014
Filed:
Sep 28, 2012
Appl. No.:
13/629891
Inventors:
Evan M. Fledell - Beaverton OR, US
Joe F. Walczyk - Tigard OR, US
Dinia P. Kitendaugh - Beaverton OR, US
International Classification:
H02J 15/00
G01R 31/26
H01R 43/00
G01R 1/067
US Classification:
32475511, 307109, 29825, 29854
Abstract:
A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.
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Evan M Fledell from Portland, OR, age ~45 Get Report