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Eriko Nurvitadhi Phones & Addresses

  • Portland, OR
  • 5672 Melvin St, Pittsburgh, PA 15217
  • Beaverton, OR
  • Corvallis, OR
  • Bronx, NY

Work

Company: Carnegie mellon university Jul 2004 Position: Phd candidate

Education

Degree: PhD School / High School: Carnegie Mellon University 2004 to 2010 Specialities: Electrical and Computer Engineering

Skills

Computer Hardware

Industries

Higher Education

Resumes

Resumes

Eriko Nurvitadhi Photo 1

Phd Candidate

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Location:
Pittsburgh, PA
Industry:
Higher Education
Work:
Carnegie Mellon University since Jul 2004
PhD Candidate

Intel May 2007 - Aug 2007
Graduate Student Intern at Strategic CAD Lab

Intel Jun 2003 - Jun 2004
Graduate Student Intern at Microprocessor Research Lab

Oregon State University Sep 2001 - Jun 2003
Graduate Research/Teaching Assistant

Mentor Graphics Jun 2001 - Sep 2001
High Level Synthesis Intern
Education:
Carnegie Mellon University 2004 - 2010
PhD, Electrical and Computer Engineering
Oregon State University 2003 - 2004
MBA
Oregon State University 2002 - 2004
MS, Electrical and Computer Engineering
Oregon State University 1997 - 2003
BA, International Studies
Oregon State University 1997 - 2002
BS, Computer Science
Oregon State University 1997 - 2001
BS, Electrical and Electronic Engineering
Oregon State University 1997 - 2001
BS, Computer Engineering
Skills:
Computer Hardware

Publications

Us Patents

Synthesis System For Pipelined Digital Circuits

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US Patent:
20110307688, Dec 15, 2011
Filed:
Jun 10, 2011
Appl. No.:
13/158081
Inventors:
Eriko Nurvitadhi - Pittsburgh PA, US
James C. Hoe - Pittsburgh PA, US
Assignee:
Carnegie Mellon University - Pittsburgh PA
International Classification:
G06F 9/38
US Classification:
712219, 712E09045
Abstract:
Computer-implemented methods and systems for synthesizing a hardware description for a pipelined datapath for a digital circuit. A transactional datapath specification framework and a transactional design automation system automatically synthesize pipeline implementations. The transactional datapath specification framework captures an abstract datapath, whose execution semantics is interpreted as a sequence of “transactions” where each transaction reads the state values left by the preceding transaction and computes a new set of state values to be seen by the next transaction. The transactional datapath specification framework exposes sufficient information about state accesses that can occur in a datapath, which is necessary for performing precise data hazards analysis, and eventually pipeline synthesis.

Specialized Fixed Function Hardware For Efficient Convolution

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US Patent:
20220391679, Dec 8, 2022
Filed:
Aug 11, 2022
Appl. No.:
17/886055
Inventors:
- Santa Clara CA, US
Xiaoming Chen - Shanghai, CN
Dhawal Srivastava - Phoenix AZ, US
Anbang Yao - Beijing, CN
Kevin Nealis - San Jose CA, US
Eriko Nurvitadhi - Portland OR, US
Sara S. Baghsorkhi - San Jose CA, US
Balaji Vembu - Folsom CA, US
Tatiana Shpeisman - Menlo Park CA, US
Ping T. Tang - Edison NJ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/063
G06N 3/04
G06F 9/30
G06F 9/38
G06T 1/20
G06N 3/08
G06F 16/17
Abstract:
One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

Instructions And Logic To Perform Floating Point And Integer Operations For Machine Learning

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US Patent:
20220357945, Nov 10, 2022
Filed:
Jun 7, 2022
Appl. No.:
17/834482
Inventors:
- Santa Clara CA, US
Mark A. Anders - Hillsboro OR, US
Sanu K. Mathew - Hillsboro OR, US
Anbang Yao - Beijing, CN
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael S. Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Tatiana Shpeisman - Menlo Park CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Nicolas C. Galoppo Von Borries - Portland OR, US
Eriko Nurvitadhi - Hillsboro OR, US
Rajkishore Barik - Santa Clara CA, US
Tsung-Han Lin - Campbell CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Sanjeev Jahagirdar - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/30
G09G 5/393
G06F 9/38
G06F 7/483
G06F 7/544
G06N 3/04
G06N 3/063
G06N 3/08
Abstract:
One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

Efficient Thread Group Scheduling

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US Patent:
20220350651, Nov 3, 2022
Filed:
May 17, 2022
Appl. No.:
17/746201
Inventors:
- Santa Clara CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Rajkishore Barik - Santa Clara CA, US
Eriko Nurvitadhi - Hillsboro OR, US
Nicolas Galoppo Von Borries - Portland OR, US
Tsung-Han Lin - Campbell CA, US
Sanjeev Jahagirdar - Folsom CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/48
G06T 1/20
Abstract:
A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Compute Optimization Mechanism For Deep Neural Networks

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US Patent:
20220335562, Oct 20, 2022
Filed:
May 11, 2022
Appl. No.:
17/741934
Inventors:
- Santa Clara CA, US
Narayan Srinivasa - Portland OR, US
Feng Chen - Shanghai, CN
Joydeep Ray - Folsom CA, US
Ben J. Ashbaugh - Folsom CA, US
Nicolas C. Galoppo Von Borries - Portland OR, US
Eriko Nurvitadhi - Hillsboro OR, US
Balaji Vembu - Folsom CA, US
Tsung-Han Lin - Campbell CA, US
Kamal Sinha - Rancho Cordova CA, US
Rajkishore Barik - Santa Clara CA, US
Sara S. Baghsorkhi - San Jose CA, US
Justin E. Gottschlich - Santa Clara CA, US
Altug Koker - El Dorado Hills CA, US
Nadathur Rajagopalan Satish - Santa Clara CA, US
Farshad Akhbari - Chandler AZ, US
Dukhwan Kim - San Jose CA, US
Wenyin Fu - Folsom CA, US
Travis T. Schluessler - Hillsboro OR, US
Josh B. Mastronarde - Sacramento CA, US
Linda L. Hurd - Cool CA, US
John H. Feit - Folsom CA, US
Jeffery S. Boles - Folsom CA, US
Adam T. Lake - Portland OR, US
Karthik Vaidyanathan - Berkeley CA, US
Devan Burke - Portland OR, US
Subramaniam Maiyuran - Gold River CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 1/20
G06F 9/455
G06F 9/50
G06N 3/04
G06N 3/063
G06N 3/08
Abstract:
Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Neural Network Scheduling Mechanism

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US Patent:
20220327357, Oct 13, 2022
Filed:
Apr 18, 2022
Appl. No.:
17/723074
Inventors:
- Santa Clara CA, US
Nadathur Rajagopalan Satish - Santa Clara CA, US
Jeremy Bottleson - Rancho Cordova CA, US
Farshad Akhbari - Chandler AZ, US
Eriko Nurvitadhi - Hillsboro OR, US
Chandrasekaran Sakthivel - Sunnyvale CA, US
Barath Lakshmanan - Chandler AZ, US
Jingyi Jin - Folsom CA, US
Justin E. Gottschlich - Santa Clara CA, US
Michael Strickland - Sunnyvale CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/04
G06F 9/50
G06N 3/063
G06N 3/08
Abstract:
An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

Two-Stage Decompression Pipeline For Non-Uniform Quantized Neural Network Inference On Reconfigurable Hardware

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US Patent:
20220300795, Sep 22, 2022
Filed:
Jun 9, 2022
Appl. No.:
17/836523
Inventors:
- Santa Clara CA, US
Nilesh Jain - Portland OR, US
Pasquale Cocchini - Portland OR, US
Eriko Nurvitadhi - Hillsboro OR, US
International Classification:
G06N 3/063
G06F 17/16
Abstract:
Systems, apparatuses and methods may provide for technology that includes a performance-enhanced decompression pipeline having first decoder hardware to convert variable length weights to fixed length keys, wherein the variable length weights are non-uniform quantization values, and second decoder hardware to convert the fixed length keys to bit value. In one example, the first length keys are compressed representations of the variable length weights and the bit values are bit accurate representations of the fixed length keys.

Data Operations And Finite State Machine For Machine Learning Via Bypass Of Computational Tasks Based On Frequently-Used Data Values

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US Patent:
20220253317, Aug 11, 2022
Filed:
Mar 1, 2022
Appl. No.:
17/683564
Inventors:
- Santa Clara CA, US
Nadathur Rajagopalan Satish - Santa Clara CA, US
Jeremy Bottleson - Rancho Cordova CA, US
Farshad Akhbari - Chandler AZ, US
Eriko Nurvitadhi - Hillsboro OR, US
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Joydeep Ray - Folsom CA, US
Balaji Vembu - Folsom CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Sanjeev Jahagirdar - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/38
G06T 1/20
G06F 9/448
Abstract:
A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.
Eriko J Nurvitadhi from Portland, OR, age ~46 Get Report