Erick Labarca Phones & Addresses
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14150 Wunderlich Dr, Houston, TX 77069
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Wichita, KS
Publications
Us Patents
Data Array Having Redundancy Messaging Between Array Controllers Over The Host Bus
View pageUS Patent:
20030126347, Jul 3, 2003
Filed:
Dec 27, 2001
Appl. No.:
10/034138
Inventors:
Greg Pellegrino - Tomball TX, US
Erick Labarca - Houston TX, US
Erick Labarca - Houston TX, US
International Classification:
G06F013/20
US Classification:
710/313000
Abstract:
A data array system, and inter-controller-link messaging method, for controlling redundant access to a storage device and providing inter-controller communication without a dedicated controller link. The host has a host bus, such as a PCI bus, and the system includes an active and a standby controller that are linked to the host bus and use the host bus for an inter-controller-link. A messaging mechanism transmits messages and data over the host bus from the active to the standby controller. The standby controller includes message and data buffers for storing the messages and data written and a message queue in which the active controller writes a signal identifier indicating that a new message has been written and defining the message for processing by the standby controller (such as a message-only transfer, a partial or all data transfer, or as a data-only transfer).
Translating Device Adapter Having A Common Command Set For Interfacing Multiple Types Of Redundant Storage Devices To A Host Processor
View pageUS Patent:
20040225775, Nov 11, 2004
Filed:
Mar 1, 2001
Appl. No.:
09/797096
Inventors:
Greg Pellegrino - Tomball TX, US
Choon Tan - Houston TX, US
Richard Gunlock - Houston TX, US
Matthew Curley - Austin TX, US
Erick Labarca - Houston TX, US
Choon Tan - Houston TX, US
Richard Gunlock - Houston TX, US
Matthew Curley - Austin TX, US
Erick Labarca - Houston TX, US
International Classification:
G06F013/00
G06F013/38
G06F013/38
US Classification:
710/200000
Abstract:
A translating host bus interface adapter is capable of connecting a computer system as a compute node to a storage area network. The adapter has a processor and a memory system containing firmware for execution in the processor. The host bus adapter is capable of recognizing first and second types of redundant storage accessible over the storage area network and translating generic storage commands into translated commands suitable for communicating with either type of redundant storage, and forwarding the translated commands onto the storage area network. The translating host bus adapter is also capable of constructing and maintaining a mirrored dataset comprising copies on redundant storage systems of either or both types.