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Eric Soenen Phones & Addresses

  • Pflugerville, TX
  • 4501 Tortuga Cv, Austin, TX 78731 (512) 243-5998
  • Comstock, TX
  • Round Rock, TX
  • 4429 Barwyn Ln, Plano, TX 75093 (972) 985-4687
  • 2605 Winding Hollow Ln, Plano, TX 75093 (972) 985-4687
  • 4220 Donnington Dr, Plano, TX 75093
  • Del Rio, TX
  • Danville, CA
  • 4501 Tortuga Cv, Austin, TX 78731 (214) 450-3101

Work

Company: Tsmc Position: Director, austin design center

Education

School / High School: Texas A&M University

Skills

Semiconductors • Design

Industries

Semiconductors

Resumes

Resumes

Eric Soenen Photo 1

Director, Austin Design Center

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Location:
Austin, TX
Industry:
Semiconductors
Work:
TSMC
Director, Austin Design Center
Education:
Texas A&M University
Skills:
Semiconductors
Design

Business Records

Name / Title
Company / Classification
Phones & Addresses
Eric Soenen
Director, President, Treasurer
NON-TRIVIAL CREATIONS, INC
Computer Related Services · Nonclassifiable Establishments · Computer Related Services, NEC
4501 Tortuga Cv, Austin, TX 78731
2605 Winding Holw Ln, Plano, TX 75093
(972) 985-4687

Publications

Us Patents

Method And Apparatus For Obtaining Linearity In A Pipelined Analog-To-Digital Converter

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US Patent:
6373424, Apr 16, 2002
Filed:
Dec 18, 2000
Appl. No.:
09/740350
Inventors:
Eric G. Soenen - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 138
US Classification:
341161, 341118, 341172, 341120
Abstract:
A pipelined analog-to-digital converter system ( ) is responsive to an analog input signal ( ). The system includes four pipeline stages ( ), which each produce a respective digital output ( ) that is coupled to a combining circuit ( ). The combining circuit generates the digital output ( ) of the system. Each pipeline stage includes an analog-to-digital converter ( ), which generates the digital output for that stage. A shuffler circuit ( ) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches ( ) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal ( ) from that stage.

System And Method For Optimizing Power In Pipelined Data Converters

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US Patent:
6501411, Dec 31, 2002
Filed:
May 3, 2001
Appl. No.:
09/848635
Inventors:
Karthikeyan Soundarapandian - Dallas TX
Eric G. Soenen - Plano TX
T. Lakshmi Viswanathan - Addision TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 138
US Classification:
341161, 327102
Abstract:
A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Complete Cds/Pga Sample And Hold Amplifier

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US Patent:
6529237, Mar 4, 2003
Filed:
Nov 10, 1998
Appl. No.:
09/189237
Inventors:
Arash Loloee - Plano TX
Eric G. Soenen - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04N 5217
US Classification:
348241, 348243, 348308, 348533
Abstract:
A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch ( ) to clamp the DC level therein for a given pixel. A switch ( ) then samples the reset level onto a sampling capacitor ( ), and a switch ( ) thereafter samples the video signal onto one plate of a capacitor ( ). The lower plates of the capacitors ( ) and ( ) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier ( ). An offset is provided by a programmable DAC ( ) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors ( ) and ( ) can be varied to vary the gain of the amplifier.

Digital Control Of Power Converters

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US Patent:
7834604, Nov 16, 2010
Filed:
Aug 25, 2008
Appl. No.:
12/197790
Inventors:
Eric Soenen - Austin TX, US
Alan Roth - Austin TX, US
Martin Kinyua - Austin TX, US
Justin Shi - Austin TX, US
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu
International Classification:
G05F 1/40
US Classification:
323282
Abstract:
A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

Class D Amplifier Control Circuit And Method

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US Patent:
7990215, Aug 2, 2011
Filed:
Aug 17, 2010
Appl. No.:
12/858310
Inventors:
Eric Soenen - Austin TX, US
Alan Roth - Austin TX, US
Justin Shi - Austin TX, US
Martin Kinyua - Austin TX, US
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu
International Classification:
H03F 3/217
US Classification:
330251, 330 10
Abstract:
Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.

Digital Control Of Power Converters

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US Patent:
8004259, Aug 23, 2011
Filed:
Oct 22, 2008
Appl. No.:
12/256300
Inventors:
Eric Soenen - Austin TX, US
Alan Roth - Austin TX, US
Martin Kinyua - Austin TX, US
Justin Shi - Austin TX, US
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu
International Classification:
G05F 1/40
US Classification:
323282
Abstract:
A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

Noise Shaping For Digital Pulse-Width Modulators

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US Patent:
8299946, Oct 30, 2012
Filed:
Dec 3, 2010
Appl. No.:
12/959869
Inventors:
Eric Soenen - Austin TX, US
Alan Roth - Leander TX, US
Martin Kinyua - Austin TX, US
Justin Shi - Austin TX, US
Justin Gaither - Austin TX, US
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd.
International Classification:
H03M 3/00
US Classification:
341143, 341144, 341152
Abstract:
A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i. e. , the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected.

Amplifier With Digital Input And Digital Pwm Control Loop

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US Patent:
8305246, Nov 6, 2012
Filed:
Sep 28, 2010
Appl. No.:
12/892487
Inventors:
Martin Kinyua - Austin TX, US
Eric Soenen - Austin TX, US
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd.
International Classification:
H03M 3/02
US Classification:
341143, 341150
Abstract:
A class D amplifier is configured to accept a digital input signal wherein the control loop of the class D amplifier employs a hybrid filter merged with the front-end of a sigma-delta ADC converter. The term hybrid refers to the filter using both digital and analog components in which the digital delay elements serve as shift registers while the filter coefficients are analog. The filter converts the digital PDM data into a step-wise sinusoidal signal. The sigma-delta ADC receiving a feedback signal subtracts the step-wise sinusoidal signal from the continuous sinusoidal signal and converts the result to a digital PDM signal, without decimation, which passes through a digital filter, a PWM generator, and a pre-driver, to provide power to the load.
Eric G Soenen from Pflugerville, TX, age ~60 Get Report