Search

Ephrem Gelaee Gebreselasie

from South Burlington, VT
Age ~58
Get Report
Also known as:
Ephrem G Gebreselasie, Ephen Gezaee Gebreselasie, Ephram Gebreselasie, M E, Ephrem E
Phone and address:
35 Elsom Pkwy, Burlington, VT 05403
(802) 865-7920
Connected to:
Amanuel Gebreselassie, 43Haile B Gebreselassie, 70Mekdes A Gebreselassie, 54Rahel Gebreselassie, 45Gerawork Gebreslassie, 62Zelalem D Gebrewold, 55Amanuel M Gebreyesus, 39Kulleni Gebreyes, 52Rahel P Gebreyesus, 50Tigist Gebreyes, 48

Ephrem Gebreselasie Phones & Addresses

  • 35 Elsom Pkwy, South Burlington, VT 05403 (802) 865-7920
  • S Burlington, VT
  • 174 Kelady Dr, Shelburne, VT 05482
  • Kansas City, MO
  • 5146 11Th St, Phoenix, AZ 85013 (602) 230-8505
  • S Burlington, VT

Work

Company: Ibm Feb 2001 Position: Esd and latchup device design and application engineer

Education

Degree: MS School / High School: University of Vermont 2006 to 2009 Specialities: Electrical Engineer

Skills

Cmos • Semiconductors • Ic • Circuit Design • Eda • Vlsi • Simulations • Asic • Mixed Signal • Analog • Cadence Virtuoso • Verilog • Soc • Analog Circuit Design • Physical Design • Hardware Architecture • Spice • Esd Control • Very Large Scale Integration • Signal Integrity • Application Specific Integrated Circuits

Languages

English • Amharic • Swahili

Interests

Children • Economic Empowerment • Civil Rights and Social Action • Environment • Education • Poverty Alleviation • Science and Technology • Human Rights • Animal Welfare • Arts and Culture • Health

Industries

Information Technology And Services

Resumes

Resumes

Ephrem Gebreselasie Photo 1

Senior Member Of Technical Staff

View page
Location:
35 Elsom Pkwy, South Burlington, VT 05403
Industry:
Information Technology And Services
Work:
IBM since Feb 2001
ESD and Latchup Device Design and Application Engineer
Goodrich Sep 1992 - Feb 1998
Technician
Education:
University of Vermont 2006 - 2009
MS, Electrical Engineer Arizona State University
BS, Electrical Engineering
Skills:
Cmos
Semiconductors
Ic
Circuit Design
Eda
Vlsi
Simulations
Asic
Mixed Signal
Analog
Cadence Virtuoso
Verilog
Soc
Analog Circuit Design
Physical Design
Hardware Architecture
Spice
Esd Control
Very Large Scale Integration
Signal Integrity
Application Specific Integrated Circuits
Interests:
Children
Economic Empowerment
Civil Rights and Social Action
Environment
Education
Poverty Alleviation
Science and Technology
Human Rights
Animal Welfare
Arts and Culture
Health
Languages:
English
Amharic
Swahili

Publications

Us Patents

Vertical Parallel Plate Capacitor Structures

View page
US Patent:
7876547, Jan 25, 2011
Filed:
May 30, 2007
Appl. No.:
11/755502
Inventors:
Ephrem G. Gebreselasie - Shelburne VT, US
Zhong-Xiang He - Essex Junction VT, US
Steven H. Voldman - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01G 4/008
H01G 4/005
H01G 4/38
US Classification:
361303, 361305, 361328, 361329, 257306, 257307, 257595, 257E27048
Abstract:
Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.

Electrostatic Discharge Structures And Methods Of Manufacture

View page
US Patent:
8054597, Nov 8, 2011
Filed:
Jun 23, 2009
Appl. No.:
12/489774
Inventors:
Ephrem G. Gebreselasie - South Burlington VT, US
Steven H. Voldman - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02H 3/22
US Classification:
361 56, 361111
Abstract:
Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

Metal Gate Integration Structure And Method Including Metal Fuse, Anti-Fuse And/Or Resistor

View page
US Patent:
8159040, Apr 17, 2012
Filed:
May 13, 2008
Appl. No.:
12/119526
Inventors:
Douglas D. Coolbaugh - Highland NY, US
Ebenezer E. Eshun - Newburgh NY, US
Ephrem G. Gebreselasie - South Burlington VT, US
Zhong-Xiang He - Essex Junction VT, US
Herbert Lei Ho - New Windsor NY, US
Chandrasekharan Kothandaraman - Hopewell Junction NY, US
Dan Moy - Bethel CT, US
Robert Mark Rassel - Colchester VT, US
John Matthew Safran - Wappingers Falls NY, US
Kenneth Jay Stein - Sandy Hook CT, US
Norman Whitelaw Robson - Hopewell Junction NY, US
Ping-Chuan Wang - Hopewell Junction NY, US
Hongwen Yan - Somers NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/00
US Classification:
257529, 257530, 257536
Abstract:
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Vertical Silicide E-Fuse

View page
US Patent:
8530319, Sep 10, 2013
Filed:
Oct 14, 2010
Appl. No.:
12/904435
Inventors:
Ephrem G. Gebreselasie - South Burlington VT, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US
Ping-Chuan Wang - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
H01L 21/44
US Classification:
438379, 438600, 438601
Abstract:
An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.

Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage

View page
US Patent:
8586423, Nov 19, 2013
Filed:
Jun 24, 2011
Appl. No.:
13/168232
Inventors:
Renata Camillo-Castillo - Essex Junction VT, US
Erik M. Dahlstrom - Burlington VT, US
Ephrem G. Gebreselasie - South Burlington VT, US
Richard A. Phelps - Colchester VT, US
Yun Shi - South Burlington VT, US
Andreas Stricker - Milpitas CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/02
US Classification:
438133, 438135, 438303, 438305, 438309, 257E21389, 257E29215, 257E29225
Abstract:
Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Stress Enhanced Ldmos Transistor To Minimize On-Resistance And Maintain High Breakdown Voltage

View page
US Patent:
8598660, Dec 3, 2013
Filed:
Jun 1, 2011
Appl. No.:
13/150612
Inventors:
Renata Camillo-Castillo - Essex Junction VT, US
Erik Mattias Dahlstrom - Burlington VT, US
Ephrem G. Gebreselasie - South Burlington VT, US
Richard A. Phelps - Colchester VT, US
Jed Hickory Rankin - Richmond VT, US
Yun Shi - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119
US Classification:
257343, 257335, 257401, 257341
Abstract:
A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i. e. , on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

Product And Method For Integration Of Deep Trench Mesh And Structures Under A Bond Pad

View page
US Patent:
8044510, Oct 25, 2011
Filed:
Oct 22, 2008
Appl. No.:
12/256089
Inventors:
Ephrem G. Gebreselasie - Shelburne VT, US
William T. Motsiff - Essex Junction VT, US
Wolfgang Sauter - Richmond VT, US
Steven H. Voldman - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/48
US Classification:
257734, 257510
Abstract:
A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.

Product And Method For Integration Of Deep Trench Mesh And Structures Under A Bond Pad

View page
US Patent:
20060246682, Nov 2, 2006
Filed:
Apr 28, 2005
Appl. No.:
10/908118
Inventors:
Ephrem Gebreselasie - Shelburne VT, US
William Motsiff - Essex Junction VT, US
Wolfgang Sauter - Richmond VT, US
Steven Voldman - South Burlington VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 21/76
US Classification:
438424000
Abstract:
A method of integrating circuit components under bond pads includes establishing a trench border on a circuit element and synthesizing a set of trench mesh edges of a trench mesh to be coincident with the trench border on the circuit element. The method further includes eliminating a trench mesh contained within the trench border of the trench circuit element.
Control profile
Ephrem Gelaee Gebreselasie from South Burlington, VT, age ~58 Get Report