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Emil A Lambrache

from Chandler, AZ
Age ~64
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Connected to:
Guy Lambraia, 59John H Lambrakis, 48Alexander C Lambrecht, 30Aron A Lambrecht, 40Beth K Lambrecht, 40Cecilia Lambrecht, 88Damaris I Lambrecht, 41Dan A Lambrecht, 64Elmer J Lambrecht, 110Fred W Lambrecht, 59

Emil Lambrache Phones & Addresses

  • Chandler, AZ
  • Prescott, AZ
  • Gilbert, AZ
  • Campbell, CA
  • San Jose, CA
  • Hauppauge, NY
  • Colorado Springs, CO

Work

Company: Microchip technology Feb 2020 Position: Senior technical staff architect

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University “Politehnica” Bucharest, Romania 1997 to 2000 Specialities: Architecture, Design

Skills

Analog Circuit Design • Digital Design • Flash and Eeprom Design • Cadence Skill • Integrated Circuit Design • Analog • Soc • Verilog • Semiconductors • Embedded Systems • Static Timing Analysis

Languages

Romanian • German

Interests

Science and Technology • Education • Arts and Culture

Industries

Semiconductors

Resumes

Resumes

Emil Lambrache Photo 1

Senior Technical Staff Architect

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Microchip Technology
Senior Technical Staff Architect
Arm Jan 2017 - Nov 2018
Principal Engineer
Atmel Corporation Jul 1993 - Sep 2012
Design Director
National Semiconductor Jun 1992 - Jun 1993
Senior Design Engineer
Seeq Oct 1991 - Jun 1992
Design Engineer
Education:
University “Politehnica” Bucharest, Romania 1997 - 2000
Doctorates, Doctor of Philosophy, Architecture, Design University Politehnica Bucharest 1980 - 1985
Masters, Master of Science In Electrical Engineering, Design
Skills:
Analog Circuit Design
Digital Design
Flash and Eeprom Design
Cadence Skill
Integrated Circuit Design
Analog
Soc
Verilog
Semiconductors
Embedded Systems
Static Timing Analysis
Interests:
Science and Technology
Education
Arts and Culture
Languages:
Romanian
German

Publications

Us Patents

Dual Mode High Voltage Power Supply For Providing Increased Speed In Programming During Testing Of Low Voltage Non-Volatile Memories

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US Patent:
6597603, Jul 22, 2003
Filed:
Nov 6, 2001
Appl. No.:
10/005317
Inventors:
Emil Lambrache - Campbell CA
George Smarandoiu - San Jose CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 1604
US Classification:
36518518, 36518511, 36518523
Abstract:
A dual mode high voltage power supply circuit using an external high voltage connected through an internal high voltage switch which determines whether the memory blocks of a non-volatile memory circuit are programmed in a first mode from an internal high voltage charge pump or are programmed in a second mode from an external high voltage power supply connected in parallel to the internal high voltage charge pump. When the dual mode high voltage power supply circuit is operating in the first mode using only its internal change pump high voltage, it operates in a low power, low-speed mode, programming only one or two bits at a time but allowing the charge pump area on the die to be small. When operating in the second mode, in which the external power supply high voltage is available, eight or more bits can be written to at the same time, thus allowing a fast programming mode without the need for increasing the size of the internal charge pump, thus eliminating the additional space and cost required to increase the die area.

Serial Peripheral Interface (Spi) Apparatus With Write Buffer For Improving Data Throughput

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US Patent:
7082481, Jul 25, 2006
Filed:
Nov 25, 2003
Appl. No.:
10/722819
Inventors:
Emil Lambrache - Campbell CA, US
Benjamin F. Froemming - Campbell CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 3/00
G06F 13/12
US Classification:
710 52, 710 72
Abstract:
A serial peripheral interface apparatus has a second parallel write buffer to load in a subsequent data byte while a current data byte is being transferred serially through the apparatus instead of waiting for the previous data byte to complete the serial transfer and other commands to avoid write collision. The subsequent data byte is transferred into the second parallel write buffer only after the software driven CPU examines the status of a load enable and the status of a write buffer provided by a finite state machine controller. The software driven CPU orders the subsequent data byte to be transferred into the second parallel write buffer when the load enable is favorable and the second parallel write buffer is available. The load enable becomes favorable when a bit counter counts the first half of the transfer of the previous data set. Thus, the second parallel write buffer avoids the stretching the master clock and improves data throughput of the system.

Layout Reduction By Sharing A Column Latch Per Two Bit Lines

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US Patent:
7224610, May 29, 2007
Filed:
Jan 3, 2006
Appl. No.:
11/325132
Inventors:
Emil Lambrache - Campbell CA, US
Duncan Curry - Sunnyvale CA, US
Richard F. Pang - Milpitas CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 16/04
US Classification:
36518518, 36518525, 36518533
Abstract:
Increasing levels of integration in successive generations of semiconductor memory products are possible through minimal metal-one layout pitches. An optimal bitline layout pitch in metal-one greatly exceeds an ability to match the pitch in a layout of a corresponding array of bitline-coupling-control latches. One latch controlling coupling for two bitlines alleviates the layout problem. In order for one latch to control coupling of two bitlines a logical segregation of the addressing of even and odd bitlines is necessary along with an additional odd or even bitline selection device in series with the selection device managed by the coupling control latch. With the use of a logical-to-physical address mapping and even-odd bitline selection, a single coupling control latch is able to manage one of two bitlines at a time. One latch serving two bitlines makes possible a bitline pitch attaining a maximum layout density possible for a fabrication process.

Fast Read Port For Register File

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US Patent:
7224635, May 29, 2007
Filed:
May 17, 2005
Appl. No.:
11/130929
Inventors:
Emil Lambrache - Campbell CA, US
Benjamin F. Froemming - San Jose CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 8/00
US Classification:
36523005, 365154
Abstract:
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

Automatic Address Transition Detection (Atd) Control For Reduction Of Sense Amplifier Power Consumption

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US Patent:
7245555, Jul 17, 2007
Filed:
Dec 12, 2005
Appl. No.:
11/301040
Inventors:
Emil Lambrache - Campbell CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 8/00
US Classification:
3652335, 365233, 365194
Abstract:
An automatic ATD control circuit operates with a first delay circuit accepting a system clock pulse as an input and producing a delayed version of the system clock pulse as an output. The delay to the system clock is performed to allow a frequency comparison in a later part of the circuit. An edge detection circuit operates when the delayed system clock is received and senses an edge of the delayed system clock pulse. A pulse output from the edge detection circuit feeds into a second delay circuit; the second delay circuit produces an output pulse where a period of the pulse is determined by delay characteristics of the sense amplifier and is thus independent of system clock frequency. The pulse is compared to the system clock frequency. If the system clock frequency is above a determined frequency, the automatic ATD control circuit is disabled.

Use Of Recovery Transistors During Write Operations To Prevent Disturbance Of Unselected Cells

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US Patent:
7295466, Nov 13, 2007
Filed:
Dec 16, 2005
Appl. No.:
11/303368
Inventors:
Emil Lambrache - Campbell CA, US
Duncan Curry - Sunnyvale CA, US
Richard F. Pang - Milpitas CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 16/00
US Classification:
36518502, 36518518, 36518525, 36518528
Abstract:
A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which is coupled to a unique array bitline. A unique recovery transistor is coupled to each array bitline. The recovery transistors on odd bitlines are coupled to a first and second voltage, while the recovery transistors on even bitlines are coupled to a first and third voltage. During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled to a selected bitline is active during a recovery operation. The first voltage is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.

Double Byte Select High Voltage Line For Eeprom Memory Block

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US Patent:
7304890, Dec 4, 2007
Filed:
Dec 13, 2005
Appl. No.:
11/301401
Inventors:
Emil Lambrache - Campbell CA, US
Duncan Curry - Sunnyvale CA, US
Richard F. Pang - Milpitas CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 11/34
US Classification:
36518512, 36523805, 36518523
Abstract:
A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.

Fast Read Port For Register File

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US Patent:
7304904, Dec 4, 2007
Filed:
Apr 20, 2007
Appl. No.:
11/738207
Inventors:
Emil Lambrache - Campbell CA, US
Benjamin F. Froemming - San Jose CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 7/00
US Classification:
365205, 365207
Abstract:
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.
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Emil A Lambrache from Chandler, AZ, age ~64 Get Report