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Duane B Dimos

from Lakewood Ranch, FL
Age ~66
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Also known as:
Duane Brian Dimos, Duane C Dimos, Duane D Dimos
Related to:
Catherine A Dimos, 65Arthur D Dimos
Connected to:
Gianni C Dimos, 58Judy Dimos, 76Stephan C Dimos, 44Igor Dimoski, 36Megan R Dimotta, 35John Dimou, 43Sophia Dimou, 39Antonios N Dimoulas, 71Todd M Dimouro, 56Martin R Dimov, 44

Duane Dimos Phones & Addresses

  • Lakewood Ranch, FL
  • 902 High Hawk Trl, Euless, TX 76039 (817) 785-3234
  • 6105 Innsbrook Ct NE, Albuquerque, NM 87111
  • Upper Montclair, NJ

Work

Company: The university of texas at arlington Position: Vice president for research

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Cornell University Specialities: Materials Science, Engineering

Industries

Higher Education

Resumes

Resumes

Duane Dimos Photo 1

Vice President For Research

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Location:
Euless, TX
Industry:
Higher Education
Work:
The University of Texas at Arlington
Vice President For Research
Education:
Cornell University
Doctorates, Doctor of Philosophy, Materials Science, Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Duane B. Dimos
Research, Vice-President
University of Texas
Bus Terminal/Service Facility · Bus Terminal and Service Facilities
1225 W Mtchell St, Arlington, TX 76019
PO Box 19228, Arlington, TX 76019

Publications

Us Patents

Solid Freeform Fabrication Using Chemically Reactive Suspensions

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US Patent:
6454972, Sep 24, 2002
Filed:
Nov 22, 2000
Appl. No.:
09/721835
Inventors:
Sherry L. Morisette - Belmont MA
Joseph Cesarano, III - Albuquerque NM
Jennifer A. Lewis - Urbana IL
Duane B. Dimos - Albuquerque NM
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
B28B 704
US Classification:
264 39, 264236, 264240, 264299
Abstract:
The effects of processing parameters and suspension chemorheology on the deposition behavior of SFF components derived from polymeric-based gelcasting suspensions combines the advantages associated with SFF fabrication, including the ability to spatially tailor composition and structure as well as reduced tooling costs, with the improved handling strength afforded by the use of gel based formulations. As-cast free-formed Al O components exhibited uniform particle packing and had minimal macro-defects (e. g. , slumping or stair casing) and no discernable micro-defects (e. g. , bubbles or cracking).

Ferroelectric Capacitor With Reduced Imprint

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US Patent:
56778252, Oct 14, 1997
Filed:
Dec 28, 1995
Appl. No.:
8/579891
Inventors:
Joseph T. Evans - Albuquerque NM
William L. Warren - Albuquerque NM
Bruce A. Tuttle - Albuquerque NM
Duane B. Dimos - Albuquerque NM
Gordon E. Pike - Albuquerque NM
International Classification:
H01G 406
US Classification:
3613214
Abstract:
An improved ferroelectric capacitor exhibiting reduced imprint effects in comparison to prior art capacitors. A capacitor according to the present invention includes top and bottom electrodes and a ferroelectric layer sandwiched between the top and bottom electrodes, the ferroelectric layer comprising a perovskite structure of the chemical composition ABO. sub. 3 wherein the B-site comprises first and second elements and a dopant element that has an oxidation state greater than +4. The concentration of the dopant is sufficient to reduce shifts in the coercive voltage of the capacitor with time. In the preferred embodiment of the present invention, the ferroelectric element comprises Pb in the A-site, and the first and second elements are Zr and Ti, respectively. The preferred dopant is chosen from the group consisting of Niobium, Tantalum, and Tungsten. In the preferred embodiment of the present invention, the dopant occupies between 1 and 8% of the B-sites.

Tuneable Dielectric Films Having Low Electrical Losses

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US Patent:
60961279, Aug 1, 2000
Filed:
Feb 28, 1997
Appl. No.:
8/807334
Inventors:
Duane Brian Dimos - Albuquerque NM
Robert William Schwartz - Albuquerque NM
Mark Victor Raymond - Albuquerque NM
Husam Niman Al-Shareef - Boise ID
Carl Mueller - Lakewood CO
David Galt - Denver CO
Assignee:
Superconducting Core Technologies, Inc. - Golden CO
International Classification:
C30B 100
US Classification:
117 9
Abstract:
The present invention is directed to a method for forming dielectric thin films having substantially reduced electrical losses at microwave and millimeter wave frequencies relative to conventional dielectric thin films. The reduction in losses is realized by dramatically increasing the grain sizes of the dielectric films, thereby minimizing intergranular scattering of the microwave signal due to grain boundaries and point defects. The increase in grain size is realized by heating the film to a temperature at which the grains experience regrowth. The grain size of the films can be further increased by first depositing the films with an excess of one of the compoents, such that a highly mobile grain boundary phase is formed.

Method For Altering The Luminescence Of A Semiconductor

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US Patent:
58585591, Jan 12, 1999
Filed:
Oct 21, 1992
Appl. No.:
7/964739
Inventors:
J. Charles Barbour - Albuquerque NM
Duane B. Dimos - Albuquerque NM
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
C25F 312
US Classification:
428690
Abstract:
A method is described for altering the luminescence of a light emitting semiconductor (LES) device. In particular, a method is described whereby a silicon LES device can be selectively irradiated with a radiation source effective for altering the intensity of luminescence of the irradiated region.

Method For Forming Grain Boundary Junction Devices Using High T.sub.c Superconductors

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US Patent:
52781402, Jan 11, 1994
Filed:
Sep 16, 1992
Appl. No.:
7/945760
Inventors:
Praveen Chaudhari - Briarcliff Manor NY
Cheng-Chung J. Chi - Yorktown Heights NY
Duane B. Dimos - Montclair NJ
Jochen D. Mannhart - Metzingen, DE
Chang C. Tsuei - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B05D 512
H01B 1200
US Classification:
505 1
Abstract:
A method is disclosed for fabricating grain boundary junction devices, which comprises preparing a crystalline substrate containing at least one grain boundary therein, epitaxially depositing a high Tc superconducting layer on the substrate, patterning the superconducting layer to leave at least two superconducting regions on either side of the grain boundary and making electrical contacts to the superconducting regions so that bias currents can be produced across the grain boundary.

Grain Boundary Junction Devices Using High T.sub.c Superconductors

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US Patent:
51622980, Nov 10, 1992
Filed:
Feb 16, 1988
Appl. No.:
7/155946
Inventors:
Praveen Chaudhari - Briarcliff Manor NY
Cheng-Chung J. Chi - Yorktown Heights NY
Duane B. Dimos - Upper Montclair NJ
Jochen D. Mannhart - Metzingen, DE
Chang C. Tsuei - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01B 1200
US Classification:
257 33
Abstract:
High T. sub. c superconducting devices are described in which controlled grain boundaries in a layer of the superconductors forms a weak link or barrier between superconducting grains of the layer. A method is described for reproducibly fabricating these devices, including first preparing a substrate to include at least one grain boundary therein. A high T. sub. c superconductor layer is then epitaxially deposited on the substrate in order to produce a corresponding grain boundary in the superconducting layer. This superconducting layer is then patterned to leave at least two regions on either side of the grain boundary, the two regions functioning as contact areas for a barrier device including the grain boundary as a current flow barrier. Electrical contacts can be made to the superconducting regions so that bias currents can be produced across the grain boundary which acts as a tunnel barrier or weak link connection.

Methods Of Fabricating Applique Circuits

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US Patent:
59502924, Sep 14, 1999
Filed:
Mar 4, 1997
Appl. No.:
8/811305
Inventors:
Duane B. Dimos - Albuquerque NM
Terry J. Garino - Albuquerque NM
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
H01G 406
US Classification:
29 2542
Abstract:
Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.
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Duane B Dimos from Lakewood Ranch, FL, age ~66 Get Report