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Dieter G Ast

from Ithaca, NY
Age ~86
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Also known as:
Carol Ast, Deiter Ast, Dieter Gast, Ast Deiter
Phone and address:
9 Hunter Ln, Ithaca, NY 14850
Related to:
Ulf Ekernas, 49Stefan EkernasAnders Ekernas, 79Lars S Ekernas, 52
Connected to:
Adam M Ast, 51Ann M Ast, 79Jeff L Ast, 57Lynne S Ast, 65Marilyn K Ast, 91Randy S Ast, 64Robert S Ast, 57Taylor R Ast, 31Allison M Asta, 37Alora N Asta, 40

Dieter Ast Phones & Addresses

  • 9 Hunter Ln, Ithaca, NY 14850
  • Dryden, NY
  • Port Charlotte, FL
  • Tompkins, NY

Resumes

Resumes

Dieter Ast Photo 1

Professor

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Location:
Ithaca, NY
Industry:
Higher Education
Work:
Cornell University
Professor
Cornell University
Professor Emeritus Ms and E, Member Graduate Field Ece
Skills:
Higher Education
Dieter Ast Photo 2

Dieter Ast

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Dieter Ast Photo 3

Professor At Cornell University

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Position:
Professor at Cornell University
Location:
Ithaca, New York Area
Industry:
Semiconductors
Work:
Cornell University
Professor

Publications

Us Patents

Method For Reducing Or Eliminating Interface Defects In Mismatched Semiconductor Eiplayers

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US Patent:
50328930, Jul 16, 1991
Filed:
Jul 27, 1990
Appl. No.:
7/560249
Inventors:
Eugene A. Fitzgerald - Ithaca NY
Dieter G. Ast - Ithaca NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H01L 2904
H01L 2712
H01L 29161
H01L 2906
US Classification:
357 60
Abstract:
The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10x critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In. sub. 05 Ga. sub. 95 As/(001)GaAs interface was controlled by fabricating 2-. mu. m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500. ANG. of In. sub. 05 Ga. sub. 95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-. mu. m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100. mu. m.

Method For Reducing Or Eliminating Interface Defects In Mismatched Semiconductor Epilayers

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US Patent:
51569957, Oct 20, 1992
Filed:
Apr 12, 1991
Appl. No.:
7/684128
Inventors:
Eugene A. Fitzgerald - Ithaca NY
Dieter G. Ast - Ithaca NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H01L 2120
US Classification:
437 90
Abstract:
The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10. times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In. sub. 05 Ga. sub. 95 As/(001)GaAs interface was controlled by fabricating 2-. mu. m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500. ANG. of In. sub. 05 Ga. sub. 95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-. mu. m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100. mu. m.

Oxidizing Methods For Making Low Resistance Source/Drain Germanium Contacts

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US Patent:
55167241, May 14, 1996
Filed:
Nov 30, 1994
Appl. No.:
8/346734
Inventors:
Dieter E. Ast - Ithaca NY
William Edwards - Ithaca NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H01L 21225
US Classification:
437160
Abstract:
Low resistance contacts for microelectronic devices such as field effect transistors are formed by defining an area on a face of a semiconductor substrate, and forming a layer of an alloy on the defined area wherein the alloy comprises a first material and a second material which may be separated by a segregating step. By doping the alloy layer, a diffusion step may be used to form shallow doped regions in the semiconductor substrate. The alloy is segregated thereby forming a first layer comprising the first material on the defined area, and a second layer comprising the second material. In a preferred embodiment, the alloy comprises a compound of silicon and germanium. The alloy may be segregated by oxidizing the silicon thereby forming a first layer of germanium and a second layer of silicon dioxide. The germanium has a low bandgap thereby providing a low resistance contact to the silicon substrate. Accordingly, a low resistance contact on a shallow doped portion of a semiconductor substrate is provided.

Method Of Making Strips Of Metallic Glasses Having Uniformly Distributed Embedded Particulate Matter

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US Patent:
45236259, Jun 18, 1985
Filed:
Feb 7, 1983
Appl. No.:
6/464256
Inventors:
Dieter G. Ast - Ithaca NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
B22D 1106
B22D 1914
US Classification:
164461
Abstract:
An inert gas stream carries crystalline or amorphous phase particles which are blown at a metal melt puddle from the exterior of a crucible nozzle facing a contact surface of a continuously moving chill body and spaced slightly therefrom through which is forced a stream of molten metal. This effects homogeneous distribution of a high volume fraction of second phase particles momentarily within the melt into ribbon form prior to rapid solidification during movement away from the nozzle orifice without particle clumping. The particles may be preheated to prevent particle clumping.
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Dieter G Ast from Ithaca, NY, age ~86 Get Report