Dennis O Ouma

6683382, Jan 27, 2004

May 16, 2002

10/147384

Donald Thomas Cwynar - Orlando FL
Sudhanshu Misra - Orlando FL
Dennis Okumu Ouma - Somerset NJ
Vivek Saxena - Orlando FL
John Michael Sharpe - Allentown PA

Agere Systems Inc. - Allentown PA

H01L 2710

257759, 257775, 257758, 257700, 257701, 257208, 257760

A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

6436807, Aug 20, 2002

Jan 18, 2000

09/484310

Donald Thomas Cwynar - Orlando FL
Sudhanshu Misra - Orlando FL
Dennis Okumu Ouma - Somerset NJ
Vivek Saxena - Orlando FL
John Michael Sharpe - Allentown PA

Agere Systems Guardian Corp. - Orlando FL

H01L 214763

438619, 438618, 438620, 438756, 438926, 437225

A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.