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Demosthenes F Anastasakis

from Tigard, OR
Age ~57
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Also known as:
Demosthenes Angela Anastasakis, Demosthene F Anastasakis, Demosthenes Anastasa, Anastasakis Demosthenes
Phone and address:
10501 Naeve St, Portland, OR 97224
Related to:
Martina H AbrahamsonJosephine A MccloskeyLaurel A Edwards, 80Angela T Edwards, 55Gerald Robert Edwards, 82
Connected to:
Alexandra H Anastassopoulos, 43Amalia Anastasiadou, 43Amanda G Anastasia, 33Anastasia M Anastasia, 40Andrew M Anastasio, 56Angela Anastas, 31Annette L Anastas, 42Ashley E Anastasia, 35Audrey M Anastasi, 33Briana Anastas, 30

Demosthenes Anastasakis Phones & Addresses

  • 10501 Naeve St, Portland, OR 97224
  • Tigard, OR
  • Bend, OR
  • 2384 Schmidt Way, Beaverton, OR 97006 (503) 617-4808
  • Wilsonville, OR
  • Austin, TX

Work

Company: Synopsys Oct 1997 Position: Sr. staff r&d eng.

Education

Degree: MSEE School / High School: The University of Texas at Austin 1990 to 1992 Specialities: Computer Eng.

Skills

Eda • Formal Verification • Debugging • Verilog • C • Perl • Software Development • C++ • Logic Bist • Boundary Scan • Algorithms • Tcl • Vhdl • Software Design • Functional Verification • Microcontrollers • Python • Java • Curl

Languages

English • Greek

Industries

Semiconductors

Resumes

Resumes

Demosthenes Anastasakis Photo 1

Principal R And D Engineer

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Synopsys since Oct 1997
Sr. Staff R&D Eng.
Mentor Graphics Sep 1992 - Oct 1997
Sr. R&D Eng.
Education:
The University of Texas at Austin 1990 - 1992
MSEE, Computer Eng. National Technical University of Athens 1984 - 1989
Diploma, Electrical Engineering
Skills:
Eda
Formal Verification
Debugging
Verilog
C
Perl
Software Development
C++
Logic Bist
Boundary Scan
Algorithms
Tcl
Vhdl
Software Design
Functional Verification
Microcontrollers
Python
Java
Curl
Languages:
English
Greek

Publications

Us Patents

Hierarchical Verification For Equivalence Checking Of Designs

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US Patent:
6668362, Dec 23, 2003
Filed:
Jan 9, 2002
Appl. No.:
10/043737
Inventors:
Lisa McIlwain - Portland OR
Demosthenes Anastasakis - Tigard OR
Slawomir Pilarski - Beaverton OR
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
716 5, 716 3
Abstract:
A method and apparatus for determining equivalence between two integrated circuit device designs. Functional blocks and compare points within a first design are compared with functional blocks and compare points in a second design to determine compare points that are matched. The integrated circuit designs are traversed net-wise and cut points are inserted at compare points that are matched and that are not determined to be constant. As each design is traversed, the design is flattened such that flat copies of both integrated circuit designs are obtained (that include the inserted cut points). The flat copies of the integrated circuit designs are then compared to determine equivalence.

System And Process Of Extracting Gate-Level Descriptions From Simulation Tables For Formal Verification

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US Patent:
62471651, Jun 12, 2001
Filed:
Mar 22, 2000
Appl. No.:
9/533649
Inventors:
Peter Wohl - Williston VT
Demosthenes Anastasakis - Beaverton OR
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
716 5
Abstract:
A system and method for generating gate level descriptions tables from simulation for formal verification. Implementation libraries contain table-based descriptions of user defined primitives (UDPs), various-strength primitives, hierarchical structural cells and non-functional constructs, such as timing and simulation assertion checks. In order to use the library cells for use by test-generation (ATPG) and formal verification (FV), the present invention provides a library reader and a model builder that read in the library cells and construct gate-level models usable by ATPG processes. The present invention also provides a translator that accesses the ATPG models through an API (Application Programming Interface) interface and produces FV models that are usable by FV processes. Significantly, according to the present invention, the FV models are generated based on the ATPG models. Library cell complexities that would require different ATPG and FV models are automatically detected.

Boolean Methods For Engineering Change Order (Eco) Patch Identification

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US Patent:
20220198109, Jun 23, 2022
Filed:
Dec 22, 2021
Appl. No.:
17/558952
Inventors:
- Mountain View CA, US
Maheshwar CHANDRASEKAR - Santa Clara CA, US
Demosthenes ANASTASAKIS - Portland OR, US
Makarand PATIL - Portland OR, US
International Classification:
G06F 30/327
Abstract:
A netlist is updated based on an engineering change order (ECO) circuit network by determining primary cuts of a first network of a netlist and secondary cuts of the ECO circuit network. The primary cuts are at least a portion of the first network, and include one or more logic elements and an output node. The secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements and an output node. Further, matching cuts are determined from the primary cuts and the secondary cuts. The matching cuts include a first cut of the primary cuts and a second cut of the secondary cuts. A downward frontier of the ECO circuit network is determined from the matching cuts, and the netlist is updated based on the downward frontier.
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Demosthenes F Anastasakis from Tigard, OR, age ~57 Get Report