Deepak C Mital

8321385, Nov 27, 2012

Mar 12, 2011

13/046719

William Burroughs - Macungie PA, US
Deepak Mital - Orefield PA, US
Mohammed Reza Hakami - Bethlehem PA, US

LSI Corporation - Milpitas CA

G06F 7/00
G06F 17/00
G06F 17/30

707692, 707698, 707747

Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

8407707, Mar 26, 2013

May 18, 2010

12/782411

David P. Sonnier - Austin TX, US
Balakrishnan Sundararaman - Cedar Park TX, US
Shailendra Aulakh - Austin TX, US
Deepak Mital - Orefield PA, US

LSI Corporation - Milpitas CA

G06F 9/46

718101, 718100, 718102

Described embodiments provide a method of assigning tasks to queues of a processing core. Tasks are assigned to a queue by sending, by a source processing core, a new task having a task identifier. A destination processing core receives the new task and determines whether another task having the same identifier exists in any of the queues corresponding to the destination processing core. If another task with the same identifier as the new task exists, the destination processing core assigns the new task to the queue containing a task with the same identifier as the new task. If no task with the same identifier as the new task exists in the queues, the destination processing core assigns the new task to the queue having the fewest tasks. The source processing core writes the new task to the assigned queue. The destination processing core executes the tasks in its queues.

8499137, Jul 30, 2013

Dec 9, 2010

12/963895

Joseph Hasting - Heidelberg CT, US
Deepak Mital - Orefield PA, US

LSI Corporation - Milpitas CA

G06F 12/00

711170, 711171, 711172, 707813, 707814

Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.

8505013, Aug 6, 2013

Dec 22, 2010

12/975823

Steven Pollock - Allentown PA, US
William Burroughs - Macungie PA, US
Deepak Mital - Orefield PA, US
Te Khac Ma - Allentown PA, US
Narender Vangati - Austin TX, US
Larry King - Austin TX, US

LSI Corporation - Milpitas CA

G06F 9/46
G06F 12/06

718102, 711 5

Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

8514874, Aug 20, 2013

Dec 22, 2010

12/975880

Deepak Mital - Orefield PA, US
James Clee - Orefield PA, US

LSI Corporation - Milpitas CA

H04L 12/56

370412, 370389

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

8515965, Aug 20, 2013

Feb 23, 2012

13/403468

Deepak Mital - Orefield PA, US
Mohammed Reza Hakami - Bethlehem PA, US
William Burroughs - Macungie PA, US

LSI Corporation - Milpitas CA

G06F 17/30

707747, 707770

Described embodiments process hash operation requests of a network processor. A hash processor determines a job identifier, a corresponding hash table, and a setting of a traversal indicator for a received hash operation request that includes a desired key. The hash processor concurrently generates a read request for a first bucket of the hash table, and provides the job identifier, the key and the traversal indicator to a read return processor. The read return processor stores the key and traversal indicator in a job memory and stores, in a return memory, entries of the first bucket of the hash table. If a stored entry matches the desired key, the read return processor determines, based on the traversal indicator, whether to read a next bucket of the hash table and provides the job identifier, the matching key, and the address of the bucket containing the matching key to the hash processor.

8537832, Sep 17, 2013

Mar 12, 2011

13/046726

Jerry Pirog - Easton PA, US
Deepak Mital - Orefield PA, US
William Burroughs - Macungie PA, US

LSI Corporation - Milpitas CA

H04L 12/28

3703954, 710316, 379242

Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

8539199, Sep 17, 2013

Mar 12, 2011

13/046717

William Burroughs - Macungie PA, US
Deepak Mital - Orefield PA, US
Mohammed Reza Hakami - Bethlehem PA, US
Michael R. Betker - Orefield PA, US

LSI Corporation - Milpitas CA

G06F 12/08

711216, 707747

Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.