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Deepak Lala Phones & Addresses

  • Palo Alto, CA
  • 1293 Lennon Way, San Jose, CA 95125
  • 42205 Camino Santa Barbara, Fremont, CA 94539
  • 233 Pagosa Ct, Fremont, CA 94539 (510) 657-7460
  • 460 Cascadita Ter, Milpitas, CA 95035 (408) 946-7574
  • Warrenton, OR
  • Sunnyvale, CA
  • Tempe, AZ

Work

Company: Lsi Mar 2013 Address: Miliptas Position: Senior engineering director

Education

School / High School: Northwestern University - Kellogg School of Management 2008 to 2009

Skills

SoC • Cloud Computing • Embedded Systems • ASIC • Perl • Software Development • Semiconductors • Architecture • Distributed Systems • RTL design • FPGA • Linux • Verilog

Industries

Telecommunications

Resumes

Resumes

Deepak Lala Photo 1

Deepak Lala

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Position:
Senior Engineering Director at LSI
Location:
San Francisco Bay Area
Industry:
Telecommunications
Work:
LSI - Miliptas since Mar 2013
Senior Engineering Director
Education:
Northwestern University - Kellogg School of Management 2008 - 2009
Arizona State University 1992 - 1994
Barkatullah Vishwavidyalaya
Skills:
SoC
Cloud Computing
Embedded Systems
ASIC
Perl
Software Development
Semiconductors
Architecture
Distributed Systems
RTL design
FPGA
Linux
Verilog

Publications

Us Patents

Apparatus And Method For Determining A Cache Line In An N-Way Set Associative Cache Using Hash Functions

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US Patent:
8397025, Mar 12, 2013
Filed:
Dec 30, 2010
Appl. No.:
12/981486
Inventors:
Maghawan Punde - Pune, IN
Deepak Lala - Fremont CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711128, 711216, 711206, 711108, 707693, 707719
Abstract:
A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.

Method And System For Restoration Of A Packet Arrival Order By An Information Technology System

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US Patent:
20100080231, Apr 1, 2010
Filed:
Sep 26, 2008
Appl. No.:
12/286120
Inventors:
Deepak Lala - Fremont CA, US
Nayan Amrutlal Suthar - Pune, IN
Umesh Ramkrishnarao Kasture - Pune, IN
International Classification:
H04L 12/56
US Classification:
370394, 370412
Abstract:
A system and method for restoring the arrival order of a plurality of packets after receipt of the packets and prior to a retransmission of the plurality of packets are provided. The invented system is configured to process a first number of packets through a high latency path, and then process all remaining packets through a lower latency path. The received packets are stored after processing in a queue memory until either (a.) all of the packets processed through the high latency path are fully processed through the high latency path, or (b.) a time period of packet processing has expired. The packets stored in the queue are transmitted from the system in the order in which the packets were received by the system, and the additional data packets are retransmitted without storage in the queue memory. A method for allocating system resources for memory queue use is further provided

System And Method Of Use Of Fast Updatable Counters Using Dynamic Random Access Memories

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US Patent:
20100082876, Apr 1, 2010
Filed:
Sep 26, 2008
Appl. No.:
12/286121
Inventors:
Deepak Lala - Fremont CA, US
Umesh Ramkreshnarao Kasture - Pune, IN
International Classification:
G06F 12/06
US Classification:
711 5, 711105, 711E12084, 711E12082
Abstract:
A system and method for enabling one or more memories to maintain, update, and provide counter values. In a first version a dynamic random access memory, or DRAM, is bi-directionally communicatively coupled with a processor. The DRAM is divided into a plurality of banks. In the first version a set of subcounters is established, wherein each subcounter element is separately and singly located within a different DRAM bank. The value of a counter can be derived by reading and processing, e.g., adding, all of the values of each of an assigned set of subcounter subvalues maintained within the plurality of banks. Conversely, a counter value may be updated by updating a single assigned subcounter of a single bank. The first method allows a hosting computer to select a subcounter having a shortest access time, where the subcounter is an element of a set of subcounters assigned to maintain a given counter value.
Deepak Lala from Palo Alto, CA, age ~55 Get Report