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David M Yatim

from Austin, TX
Age ~60
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Also known as:
Dave M Yatim, David M Morillas, David S
Phone and address:
1904 Big Canyon Dr, Austin, TX 78746
(512) 582-0519
Related to:
Luis A Rapini, 50Sandra C Este, 53Serge Alin, 61Hedwig E Wenninger, 44Jean Yatim, 65Juana M Yatim, 92Jorge Yatim, 67Leyla Y Alin, 56
Connected to:
Nabil Yatim, 59Richard A Yatim, 35Ziad Y Yatim, 65Mary H Yatko, 57Stephen A Yatko, 57Paul C Yatkowski, 54Nicole B Yatman, 32Karima Yatooma, 65Monica M Yatooma, 66Paul J Yatooma, 69

David Yatim Phones & Addresses

  • 1904 Big Canyon Dr, Austin, TX 78746 (512) 582-0519
  • 1908 Wychwood Dr, Austin, TX 78746
  • 6808 Telluride Trl, Austin, TX 78749
  • 1503 Barn Swallow Dr, Austin, TX 78746 (512) 220-9606 (512) 347-1223
  • 2301 Mo Pac Cir, Austin, TX 78746 (512) 220-9606
  • Woodstock, VT

Resumes

Resumes

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David Yatim

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Location:
Austin, Texas Area
Industry:
Semiconductors
Skills:
ASIC
RTL design
SoC
Static Timing Analysis
Semiconductors
Verilog
Functional Verification
Dc
VLSI
IC
FPGA
EDA

Publications

Us Patents

Adpcm Transcoder With Integral Tone Generation And Method Therefor

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US Patent:
53848071, Jan 24, 1995
Filed:
Jul 2, 1992
Appl. No.:
7/908198
Inventors:
David Yatim - Austin TX
Luis A. Bonet - Austin TX
Jose G. Corleto - Austin TX
Michael D. Floyd - Plainfield IN
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 1406
US Classification:
375 27
Abstract:
An ADPCM transcoder (60) includes an integral tone generator (65) which inserts a linear tone signal, such as a conventional DTMF tone signal, into either the transmit or receive data stream, or both. A digital PCM input signal is first converted to a first linear signal. If tone generation is enabled for transmission, then the linear tone signal is substituted for or added to the first linear signal and provided to an ADPCM encoder (63), which provides an ADPCM output signal in response. An ADPCM decoder (66) receives an ADPCM input signal and provides a second linear input signal in response. If tone generation is enabled for reception, then the linear tone signal is substituted for or added to the second linear input signal, and converted to a digital PCM output signal. The ADPCM transcoder (60) may also be integrated with other components of a signal processing system.

Apparatus For Modulating/Demodulating Signals

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US Patent:
59635886, Oct 5, 1999
Filed:
Mar 21, 1997
Appl. No.:
8/822966
Inventors:
David Yatim - Austin TX
Jim Girardeau - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 138
H04J 300
H04M 100
H03K 300
US Classification:
375222
Abstract:
An apparatus connects a data processing system (10) with an analog telephone line and/or an ISDN line. The apparatus modulates and demodulates data from the data processing system (10) to either of the two different telephone protocols without adding unnecessary expense or noise to the system.

Multi-Rate Digital Filter Apparatus And Method For Sigma-Delta Conversion Processes

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US Patent:
57317690, Mar 24, 1998
Filed:
Dec 4, 1995
Appl. No.:
8/566639
Inventors:
James W. Girardeau - Austin TX
David Yatim - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03M 700
US Classification:
341 61
Abstract:
Data converter (10, 50, 150, 200) and method (250, 300) operate at variable sampling rates. Input gain stage (12) adjusts input bit stream (18) at an input bit rate (20) to produce gain adjusted bit stream (22). Integrator (14) and comb filter (16) operate on the gain adjusted bit stream (22) to produce a filtered bit stream (28) at an output bit rate (24). The gain of the integrator (14) and comb filter (16) pair varies with the sampling rates implemented. An input gain value of the input gain stage (12) adjusts to compensate for the gain of the integrator (14) and comb filter (16) pair to produce the filtered bit stream (28) within a predetermined dynamic range. DC offset stage (52) and output gain stage (54) provide further adjustment to the filtered bit stream (28). Data converters (10, 50) and method (250) convert data from a higher frequency bit rate to a lower frequency bit rate. Data converters (150, 200) and method (300) convert data from a lower frequency bit rate to a higher frequency bit rate.

Method And Apparatus For A Multiply And Accumulate Circuit Having A Dynamic Saturation Range

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US Patent:
56445199, Jul 1, 1997
Filed:
Apr 7, 1995
Appl. No.:
8/418355
Inventors:
David Yatim - Austin TX
James W. Girardeau - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 738
US Classification:
36473602
Abstract:
A method and apparatus for a multiply accumulate circuit (10) having a programmable saturation value is accomplished by providing saturation logic (20) that receives a saturation range signal (32) from a Digital Signal Processor (DSP) programmer. The saturation range signal (32) is then converted to a selected saturation value (34) and provided as an input to the saturation logic (20). The saturation logic (20) utilizes the selected saturation value (34) to establish an intermediate saturation value (30). For each intermediate resultant generated by the multiply and accumulate circuit (10), the intermediate resultant is compared with the intermediate saturation value (30). When the intermediate resultant compares unfavorably to the intermediate saturation value (30), a saturation default value (42) is supplied to the accumulator register. Additionally, the final accumulate result is compared against a final saturation value, and, if unfavorable, a saturation value is provided as the final result.

Adpcm Decoder With An Integral Digital Receive Gain And Method Therefor

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US Patent:
52590011, Nov 2, 1993
Filed:
Dec 17, 1991
Appl. No.:
7/810775
Inventors:
Jose G. Corleto - Austin TX
Luis A. Bonet - Austin TX
David Yatim - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 1406
US Classification:
375 27
Abstract:
An integral digital receive gain (44) for a G. 721 or G. 726 ADPCM decoder (28a) or the like in an application such as a CT-2 handset (20) allows digital volume control without the need for external components. The digital receive gain (44) receives a reconstructed signal s. sub. r (k) and a variable gain factor. The integral digital receive gain (44) multiplies the reconstructed signal by the gain factor and provides the result as an input to an output PCM format conversion (45). The digital receive gain (44) also disables a synchronous coding adjustment (46) if a gain setting other than unity gain is detected.

Digital Signal Processor For Executing Multiple Instruction Words

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US Patent:
58261001, Oct 20, 1998
Filed:
Nov 4, 1996
Appl. No.:
8/743605
Inventors:
Luis A. Bonet - Austin TX
David Yatim - Austin TX
James W. Girardeau - Austin TX
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
G06F 1578
US Classification:
39580033
Abstract:
A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Method And Apparatus For Noise Burst Detection In A Signal Processor

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US Patent:
53195736, Jun 7, 1994
Filed:
Jan 15, 1992
Appl. No.:
7/821111
Inventors:
Jose G. Corleto - Austin TX
Luis A. Bonet - Austin TX
David Yatim - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06K 940
H04B 1406
H04B 1500
US Classification:
364514
Abstract:
A signal processor such as an ADPCM decoder (28b) receives an input signal. As part of the CCITT Recommendation G. 726 algorithm, ADPCM decoder (28b) processes the input signal to provide a linear reconstructed signal s. sub. r (k). When enabled, a noise detector (50) samples the reconstructed signal s. sub. r (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of the reconstructed signal s. sub. r (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. This calculation prevents the need for time-consuming division operation which is difficult for high-performance digital signal processors (70).

Method And Apparatus For Interpolation And Noise Shaping In A Signal Converter

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US Patent:
56063199, Feb 25, 1997
Filed:
Aug 7, 1995
Appl. No.:
8/512251
Inventors:
David Yatim - Austin TX
James W. Girardeau - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03M 166
US Classification:
341144
Abstract:
A D/A converter (10) converts a digitized analog signal (32) to an analog signal (50). The D/A converter (10) includes first filtering stage (12), second filtering stage (14), and reduced-bit D/A converter (16). The first filtering stage (12) operates at a first sampling rate (25), interpolates the digitized analog signal (32) from an initial sampling rate to a first sampling rate (25), performs an anti-alias filter, and performs a first comb filtering function. The second filtering stage (14) operates at a second sampling rate (46), interpolates the digitized analog signal (32) to the second sampling rate (46), performs a second comb filtering function, and performs a noise shaper filter to produce a reduced-bit second sampling rate signal (48). The reduced-bit D/A converter (16) converts the second sampling rate signal (48) to an analog signal (50).
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David M Yatim from Austin, TX, age ~60 Get Report