David E Dunn

6421635, Jul 16, 2002

Nov 2, 1998

09/184845

Bharath Chandramohan - San Clara CA
Rupert Brauch - Palo Alto CA
David A. Dunn - San Jose CA

Hewlett-Packard Company - Palo Alto CA

G06F 945

703 26, 703 23

The invention determines whether any asynchronous signals are pending and then delivers any such pending signals to the emulated application before the control is transferred to the operating system. A first mechanism sets a global flag, and checks to determine if any signals are pending. If there are pending signals, the emulator halts the emulation of the system call, and delivers the signal to the emulated application. A second mechanism handles signals that arrive after the first mechanism has performed its check. This mechanism checks to see if the global flag is set when a signal arrives. If the flag is set, then the signal is delivered immediately. If the flag is not set, then the signal is deferred. A third mechanism establishes a watch state at the beginning of the emulation, which would be changed by any action of the operating system. When a signal comes in, the emulator checks the watch state.

7062631, Jun 13, 2006

Jul 17, 2003

10/623021

Alexander C. Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US

Transmeta Corporation - Santa Clara CA

G06F 12/00

711207, 711141, 711154

A method and system for enforcing consistent per-physical page cacheability attributes is disclosed. The method for enforcing consistent per-physical page cacheability attributes maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

7620779, Nov 17, 2009

May 22, 2006

11/439361

Alexander C. Klaiber - Mountain View CA, US
Guillermo J. Rozas - Los Gatos CA, US
David A. Dunn - Sammamish WA, US

G06F 12/00

711144

Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

7636815, Dec 22, 2009

Apr 9, 2003

10/411168

Alexander C. Klaiber - Mountain View CA, US
Guillermo J. Rozas - Los Gatos CA, US
David Dunn - Sammamish WA, US

G06F 12/00

711146

Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

7676629, Mar 9, 2010

Dec 20, 2005

11/314494

Alexander C. Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US

G06F 12/00
G06F 13/00

711118, 711141, 711154, 711200, 711207

A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

7937536, May 3, 2011

Nov 23, 2009

12/624094

Alexander C. Klaiber - Mountain View CA, US
Guillermo J. Rozas - Los Gatos CA, US
David Dunn - Sammamish WA, US

G06F 12/00

711146

Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

8117421, Feb 14, 2012

Jan 15, 2010

12/688722

Alexander C. Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US

G06F 12/00
G06F 13/00

711206, 711100, 711141, 711154, 711200

A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

8607025, Dec 10, 2013

Jan 31, 2012

13/363050

Alexander C. Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US

G06F 12/00
G06F 13/00

711206, 711100, 711117, 711154, 711200

A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.