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David A Daycock

from Boise, ID
Age ~46
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Also known as:
David Allen Daycock, David M Daycock, David K
Phone and address:
5346 Keybridge Dr, Boise, ID 83703
Related to:
Cameron N Prince, 39Kenneth W Daycock, 62Dean D Kreger, 65Melissa A Daycock, 51James V Bellew, 42Dorothea E Kreger, 91Cheryl L Daycock, 65Mitchell W Kreger, 93
Connected to:
Elso C Dayday, 70Al S Daye, 80Amanda J Daye, 40Ashley P Daye, 65Athalen Daye, 79Bernard E Daye, 33Brenda S Daye, 68Brian R Daye, 61Chelsea S Daye, 33Eureka C Daye, 65

David Daycock Phones & Addresses

  • 5346 Keybridge Dr, Boise, ID 83703
  • 2840 Cherry Ct, Boise, ID 83705 (208) 424-0909
  • Delaware Water Gap, PA
  • 2147 Fountain St, Allentown, PA 18103
  • Nora, IL
  • Barnesville, PA

Education

Degree: High school graduate or higher

Resumes

Resumes

David Daycock Photo 1

Director Of Process Integation And Device Technology

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology Jan 2017 - Jan 2019
Process Integration Manager
Micron Technology Jan 2017 - Jan 2019
Director of Process Integation and Device Technology
Micron Technology Jan 2016 - Jan 2017
Array Integration Lead
Micron Technology 2009 - Jan 2016
Principal Process Integration Engineer
Micron Technology 2006 - 2009
Development Engineer
Education:
Bucknell University 1996 - 2000
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Semiconductors
Jmp
Design of Experiments
Engineering
Integration Engineering
Microfabrication
Spc
Perl
Python
Css
Jquery
Html 5
Vba
David Daycock Photo 2

Development Engineer At Micron Technology

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Location:
Boise, Idaho Area
Industry:
Semiconductors
Experience:
Micron Technology (Public Company; Semiconductors industry): Development Engineer,  (-) Tyco Healthcare/JT Baker (Semiconductors industry): Applications Engineer,  (2000-2003) 

Publications

Us Patents

Method Of Reducing Damage To An Electron Beam Inspected Semiconductor Substrate, And Methods Of Inspecting A Semiconductor Substrate

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US Patent:
8563435, Oct 22, 2013
Filed:
Sep 13, 2012
Appl. No.:
13/615155
Inventors:
David A. Daycock - Boise ID, US
Paul A. Morgan - Kuna ID, US
Shawn D. Lyonsmith - Boise ID, US
Curtis R. Olson - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438692, 438 14, 257E21521
Abstract:
Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.

Method Of Reducing Electron Beam Damage On Post W-Cmp Wafers

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US Patent:
20080076263, Mar 27, 2008
Filed:
Sep 21, 2006
Appl. No.:
11/525492
Inventors:
David A. Daycock - Boise ID, US
Paul A. Morgan - Kuna ID, US
Shawn D. Lyonsmith - Boise ID, US
Curtis R. Olson - Boise ID, US
International Classification:
H01L 21/31
US Classification:
438758
Abstract:
Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.

Forming Terminations In Stacked Memory Arrays

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US Patent:
20210408029, Dec 30, 2021
Filed:
Sep 13, 2021
Appl. No.:
17/473679
Inventors:
- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US
International Classification:
H01L 27/11573
H01L 21/762
H01L 27/11578
H01L 27/1157
H01L 21/768
H01L 27/11575
Abstract:
A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Integrated Structures

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US Patent:
20210343743, Nov 4, 2021
Filed:
Jul 18, 2021
Appl. No.:
17/378743
Inventors:
- Boise ID, US
David Daycock - Boise ID, US
Kunal R. Parekh - Boise ID, US
Martin C. Roberts - Boise ID, US
Yushi Hu - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11582
H01L 29/66
H01L 29/78
Abstract:
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Integrated Assemblies Which Include Stacked Memory Decks, And Methods Of Forming Integrated Assemblies

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US Patent:
20200350333, Nov 5, 2020
Filed:
Jul 20, 2020
Appl. No.:
16/933693
Inventors:
- Boise ID, US
David Daycock - Boise ID, US
Rithu K. Bhonsle - Boise ID, US
Giovanni Mazzone - Boise ID, US
Narula Bilik - Boise ID, US
Jordan D. Greenlee - Boise ID, US
Minsoo Lee - Boise ID, US
Benben Li - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11582
H01L 27/11524
H01L 21/32
H01L 27/1157
H01L 21/311
H01L 27/11556
Abstract:
Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

Integrated Assemblies And Methods Of Forming Integrated Assemblies

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US Patent:
20200321347, Oct 8, 2020
Filed:
Jun 22, 2020
Appl. No.:
16/907858
Inventors:
- Boise ID, US
Kunal R. Parekh - Boise ID, US
Martin C. Roberts - Boise ID, US
Mohd Kamran Akhtar - Boise ID, US
Chet E. Carter - Boise ID, US
David Daycock - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11524
H01L 27/11551
H01L 27/11556
H01L 27/11582
H01L 27/11553
Abstract:
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Formation Of Termination Structures In Stacked Memory Arrays

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US Patent:
20200279867, Sep 3, 2020
Filed:
May 18, 2020
Appl. No.:
16/876896
Inventors:
- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US
International Classification:
H01L 27/11582
H01L 27/1157
H01L 27/11526
H01L 27/11556
H01L 27/11524
H01L 27/11573
Abstract:
In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

Forming Terminations In Stacked Memory Arrays

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US Patent:
20200119036, Apr 16, 2020
Filed:
Oct 15, 2018
Appl. No.:
16/159955
Inventors:
- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US
International Classification:
H01L 27/11573
H01L 27/1157
H01L 27/11578
H01L 21/762
Abstract:
A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.
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David A Daycock from Boise, ID, age ~46 Get Report