Search

Daria R Dooling

from Huntington, VT
Age ~62
Get Report
Also known as:
Daria Giess Dooling, Daria M Dooling, Daria A Dooling, Daria R Giess, Michael A Dooling, Danria Dooling, Daria G, Daria S, Dooling Daria Giess, Giess Dooling
Phone and address:
307 Pond Rd, Huntington, VT 05462
(802) 434-5192
Related to:
Joseph M Dooling
Connected to:
Aimee Dooling, 42Brian T Dooling, 59Charles T Dooling, 79Curtis B Dooling, 47Dana C Dooling, 67Ingrid R Dooling, 86Jodi K Doolinglitfin, 56Lisa Dooling, 61Matt Dooling, 61Natosha Dooling, 45

Daria Dooling Phones & Addresses

  • 307 Pond Rd, Huntington, VT 05462 (802) 434-5192 (802) 343-4120
  • Newtown, PA
  • Richmond, VT
  • 325 Stratford Dr, Southampton, PA 18966 (215) 357-2128 (215) 953-9198
  • Jericho, VT
  • Edison, NJ

Resumes

Resumes

Daria Dooling Photo 1

Software Engineer At Allscripts

View page
Location:
Burlington, Vermont Area
Industry:
Computer Software
Daria Dooling Photo 2

Daria Dooling

View page

Publications

Us Patents

Method To Partition The Physical Design Of An Integrated Circuit For Electrical Simulation

View page
US Patent:
6601025, Jul 29, 2003
Filed:
Aug 10, 1999
Appl. No.:
09/371202
Inventors:
Gary S. Ditlow - Garrison NY
Daria R. Dooling - Huntington VT
Richard L. Moore - Colchester VT
David E. Moran - South Burlington VT
Thomas W. Wilkins - Shelburne VT
Ralph J. Williams - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
703 14, 703 18, 703 22, 716 4, 716 7
Abstract:
A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.

Partitioning And Load Balancing Graphical Shape Data For Parallel Applications

View page
US Patent:
6788302, Sep 7, 2004
Filed:
Aug 3, 2000
Appl. No.:
09/631764
Inventors:
Gary S. Ditlow - Garrison NY
Daria R. Dooling - Huntington VT
David E. Moran - South Burlington VT
Ralph J. Williams - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1580
US Classification:
345505, 345544, 718105
Abstract:
The present invention divides a large graphics file into smaller âframesâ of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Autonomic Graphical Partitioning

View page
US Patent:
7051307, May 23, 2006
Filed:
Dec 3, 2003
Appl. No.:
10/707286
Inventors:
Gary S. Ditlow - Garrison NY, US
Daria R. Dooling - Huntington VT, US
Timothy G. Dunham - South Burlington VT, US
William C. Leipold - Enosburg Falls VT, US
Stephen D. Thomas - Essex Junction VT, US
Ralph J. Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 7
Abstract:
Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

Method And Apparatus To Manage Multi-Computer Demand

View page
US Patent:
7136798, Nov 14, 2006
Filed:
Jul 19, 2002
Appl. No.:
10/064486
Inventors:
Gary Ditlow - Garrison NY, US
Daria Rose Dooling - Huntington VT, US
David Erin Moran - South Burlington VT, US
Stephen D. Thomas - Essex Junction VT, US
Ralph James Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
H04L 12/28
US Classification:
703 14, 709201, 709231
Abstract:
A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Method And Apparatus To Manage Multi-Computer Supply

View page
US Patent:
7305674, Dec 4, 2007
Filed:
Aug 31, 2001
Appl. No.:
09/943829
Inventors:
Gary Ditlow - Garrison NY, US
Daria Rose Dooling - Huntington VT, US
David Erin Moran - South Burlington VT, US
Thomas Wood Wilkins - Shelburne VT, US
Ralph James Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
G06F 15/16
US Classification:
718100, 709201
Abstract:
A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Method For Visualizing Data

View page
US Patent:
7315305, Jan 1, 2008
Filed:
Jan 4, 1999
Appl. No.:
09/224696
Inventors:
Cassondra L. Crotty - Avon CT, US
Daria R. Dooling - Huntington VT, US
David E. Moran - South Burlington VT, US
Ralph J. Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06T 11/20
G09G 5/00
US Classification:
345440, 345619
Abstract:
A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

Content Based Yield Prediction Of Vlsi Designs

View page
US Patent:
7389480, Jun 17, 2008
Filed:
May 9, 2005
Appl. No.:
10/908342
Inventors:
Robert J. Allen - Jericho VT, US
Daria R. Dooling - Huntington VT, US
Jason D. Hibbeler - Williston VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Sarah C. Prue - Richmond VT, US
Ralph J. Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 19
Abstract:
A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

Method And Apparatus For Parallel Data Preparation And Processing Of Integrated Circuit Graphical Design Data

View page
US Patent:
7434185, Oct 7, 2008
Filed:
Sep 27, 2006
Appl. No.:
11/535789
Inventors:
Daria R. Dooling - Huntington VT, US
Jacek G. Smolinski - Jericho VT, US
Stephen D. Thomas - Essex Junction VT, US
Ralph J. Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 716 7, 716 11
Abstract:
A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.
Control profile
Daria R Dooling from Huntington, VT, age ~62 Get Report