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Daniel S Gitlin

from Los Angeles, CA
Age ~41
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Also known as:
Daniel Scott Gitlin, Daniel S Mount, Daniel Daniel
Related to:
Nicole Gitlin, 37Jennifer L Reichle, 54Helen GitlinGraham Gitlin, 54
Connected to:
Amy E Gitlin, 50Carol M Gitlin, 55David L Gitlin, 49Ellis A Gitlin, 71Holly Gitlin, 50Jessica Gitlin, 52Jonathan M Gitlin, 43Laura B Gitlin, 67Richard A Gitlin, 82Roman G Gitlin, 74

Daniel Gitlin Phones & Addresses

  • Los Angeles, CA
  • North Hollywood, CA
  • Hermosa Beach, CA
  • 365 Hanover Ave #106, Oakland, CA 94606
  • 2616 Elston St, Livermore, CA 94550
  • Berkeley, CA
  • San Ramon, CA
  • Long Beach, CA

Industries

Investment Banking

Resumes

Resumes

Daniel Gitlin Photo 1

Daniel Gitlin

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Location:
Greater Los Angeles Area
Industry:
Investment Banking

Business Records

Name / Title
Company / Classification
Phones & Addresses
Daniel Gitlin
Principal
Tabula Inc
Business Services at Non-Commercial Site · Nonclassifiable Establishments
679 Driscoll Ct, Palo Alto, CA 94306

Publications

Us Patents

Non-Volatile Memory Array Using Gate Breakdown Structures

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US Patent:
6522582, Feb 18, 2003
Filed:
Apr 19, 2000
Appl. No.:
09/553571
Inventors:
Kameswara K. Rao - San Jose CA
Martin L. Voogel - Los Altos CA
James Karp - Saratoga CA
Shahin Toutounchi - Pleasanton CA
Michael J. Hart - Palo Alto CA
Daniel Gitlin - Palo Alto CA
Kevin T. Look - Fremont CA
Jongheon Jeong - Campbell CA
Radko G. Bankras - Enschede, NL
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 1400
US Classification:
36518508, 36518509, 365104
Abstract:
Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e. g. sub 0. 35 micron or sub 0. 25 micron processes. Preferably, the cell structures can be fabricated using 0. 18 micron or 0. 15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located âon chipâ with an array of memory cells.

Non-Volatile Memory Array Using Gate Breakdown Structures

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US Patent:
6549458, Apr 15, 2003
Filed:
Oct 25, 2001
Appl. No.:
10/040044
Inventors:
Kameswara K. Rao - San Jose CA
Martin L. Voogel - Los Altos CA
James Karp - Saratoga CA
Shahin Toutounchi - Pleasanton CA
Michael J. Hart - Palo Alto CA
Daniel Gitlin - Palo Alto CA
Kevin T. Look - Fremont CA
Jongheon Jeong - Campbell CA
Radko G. Bankras - Enschede, NL
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 1400
US Classification:
36518508, 36518514, 36518528
Abstract:
Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0. 18 micron or 0. 15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Structures And Methods For Selectively Applying A Well Bias To Portions Of A Programmable Device

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US Patent:
6621325, Sep 16, 2003
Filed:
Sep 18, 2001
Appl. No.:
09/956203
Inventors:
Michael J. Hart - Palo Alto CA
Steven P. Young - Boulder CO
Daniel Gitlin - Palo Alto CA
Hua Shen - San Jose CA
Stephen M. Trimberger - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 301
US Classification:
327534, 36518518
Abstract:
Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e. g. , applying a positive well bias to transistors on critical paths within a users design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e. g. , CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Method Of Forming A Zener Diode

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US Patent:
6645802, Nov 11, 2003
Filed:
Jun 8, 2001
Appl. No.:
09/877690
Inventors:
Shahin Toutounchi - Pleasanton CA
Michael J. Hart - Palo Alto CA
Xin X. Wu - Fremont CA
Daniel Gitlin - Palo Alto CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 218234
US Classification:
438237, 438983, 438328
Abstract:
An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.

Ballast Resistor With Reduced Area For Esd Protection

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US Patent:
6740936, May 25, 2004
Filed:
Apr 25, 2002
Appl. No.:
10/134086
Inventors:
Daniel Gitlin - Palo Alto CA
James Karp - Saratoga CA
Jongheon Jeong - Palo Alto CA
Jan L. de Jong - Cupertino CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 2978
US Classification:
257363, 257355, 257356
Abstract:
A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Layout Correction Algorithms For Removing Stress And Other Physical Effect Induced Process Deviation

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US Patent:
7032194, Apr 18, 2006
Filed:
Feb 19, 2003
Appl. No.:
10/369888
Inventors:
Shih-Cheng Hsueh - Fremont CA, US
Xiao-Jie Yuan - Cupertino CA, US
Daniel Gitlin - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 2, 716 19
Abstract:
A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Cmos-Compatible Non-Volatile Memory Cell With Lateral Inter-Poly Programming Layer

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US Patent:
7294888, Nov 13, 2007
Filed:
Sep 30, 2005
Appl. No.:
11/240030
Inventors:
Sunhom Paak - San Jose CA, US
Boon Yong Ang - Cupertino CA, US
Hsung Jai Im - Cupertino CA, US
Daniel Gitlin - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 29/76
H01L 21/336
US Classification:
257369, 438258
Abstract:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Cmos-Compatible Non-Volatile Memory Cell With Lateral Inter-Poly Programming Layer

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US Patent:
7688639, Mar 30, 2010
Filed:
Oct 12, 2007
Appl. No.:
11/974361
Inventors:
Sunhom Paak - San Jose CA, US
Boon Yong Ang - Santa Clara CA, US
Hsung Jai Im - Cupertino CA, US
Daniel Gitlin - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 16/06
US Classification:
36518522
Abstract:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
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Daniel S Gitlin from Los Angeles, CA, age ~41 Get Report