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Liang Dai

from San Diego, CA
Age ~53
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Also known as:
Dai Liang, Dai Wu, Liang Wu
Phone and address:
5422 Foxhound Way, San Diego, CA 92130
(760) 703-9571
Related to:
James J Ames, 86James CarneyKelly J Ames, 60Bai Yun, 48Linda C Caldwell, 79
Connected to:
Aguang Dai, 43Andrew Dai, 31Bing Dai, 49Bingbing Dai, 41Clarence K Dai, 67Diana H Dai, 60Douglas Dai, 33Duong T Dai, 37Helen H Dai, 68Hongjie Dai, 58

Liang Dai Phones & Addresses

  • 5422 Foxhound Way, San Diego, CA 92130 (760) 703-9571
  • 9620 Carroll Canyon Rd, San Diego, CA 92126 (858) 578-1581
  • Irvine, CA
  • 5591 Foxtail Loop, Carlsbad, CA 92008 (760) 931-6237
  • 425 13Th St, Minneapolis, MN 55414 (612) 623-3641
  • Syracuse, NY
  • Allentown, PA

Work

Company: Qualcomm Apr 2004 Position: Principal engineer and manager

Education

Degree: Master of Business Administration, Masters School / High School: University of California, Los Angeles 2006 to 2009 Specialities: Business Administration, Management, Business Administration and Management

Skills

Cmos • Ic • Simulations • Asic • Semiconductors • Bicmos • Mixed Signal • Soc • Verilog • Vlsi • Analog • Embedded Systems • Analog Circuit Design • Eda • Cadence Virtuoso • Amplifiers • Rf • Digital Signal Processors • Pll • Phy

Languages

Mandarin

Industries

Semiconductors

Resumes

Resumes

Liang Dai Photo 1

Principal Engineer And Manager

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Location:
5591 Foxtail Loop, Carlsbad, CA 92010
Industry:
Semiconductors
Work:
Qualcomm
Principal Engineer and Manager
Prominent Communications Jan 2001 - Mar 2004
Staff Engineer
Lsi Corporation 1998 - 1999
Summer Intern
Education:
University of California, Los Angeles 2006 - 2009
Master of Business Administration, Masters, Business Administration, Management, Business Administration and Management University of Minnesota 1996 - 2000
Doctorates, Doctor of Philosophy, Electrical Engineering Peking University 1990 - 1995
Bachelors, Bachelor of Science, Physics Beijing No. 2 Middle School 1984 - 1990
University of California
Skills:
Cmos
Ic
Simulations
Asic
Semiconductors
Bicmos
Mixed Signal
Soc
Verilog
Vlsi
Analog
Embedded Systems
Analog Circuit Design
Eda
Cadence Virtuoso
Amplifiers
Rf
Digital Signal Processors
Pll
Phy
Languages:
Mandarin

Publications

Us Patents

Fast Vco Calibration For Frequency Synthesizers

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US Patent:
6859073, Feb 22, 2005
Filed:
Oct 17, 2003
Appl. No.:
10/687492
Inventors:
Liang Dai - Carlsbad CA, US
Jie Huang - San Diego CA, US
Kevin Hsi-Huai Wang - San Diego CA, US
Hung-Chuan Pai - San Diego CA, US
Assignee:
Prominent Communications, Inc. - San Diego CA
International Classification:
H03B021/00
US Classification:
327105, 331179
Abstract:
The voltage-oscillator (VCO) in a frequency synthesizer using a phase-locked loop (PLL) is calibrated during power up or channel switching. The VCO has a coarse frequency control and a fine frequency control. The coarse control consists of digital bits that are used for calibration. The coarse control is connected to the charge pump output as in a regular PLL. By searching for the optimal control setting, the center frequency of the VCO is trimmed close to the desired frequency for the PLL to lock. This allows small VCO gain without losing the tolerance of process and temperature variations. As a result, the PLL phase noise performance is improved.

Duty Cycle Correction Circuit

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US Patent:
7705647, Apr 27, 2010
Filed:
Jun 14, 2006
Appl. No.:
11/454426
Inventors:
Liang Dai - Carlsbad CA, US
Lam V. Nguyen - Cupertino CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03K 3/017
US Classification:
327175, 327170
Abstract:
A duty cycle correction circuit capable of generating a clock signal having good (e. g. , approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.

Methods And Apparatus For Dynamic Frequency Scaling Of Phase Locked Loops For Microprocessors

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US Patent:
7821350, Oct 26, 2010
Filed:
Jan 19, 2007
Appl. No.:
11/624995
Inventors:
Liang Dai - Carlsbad CA, US
Brandon Wayne Lewis - Cary NC, US
Jeffrey Todd Bridges - Raleigh NC, US
Weihua Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/04
US Classification:
331179, 331 46, 331 36 C, 331 2
Abstract:
A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

All-Digital Selectable Duty Cycle Generation

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US Patent:
8140026, Mar 20, 2012
Filed:
May 6, 2009
Appl. No.:
12/436288
Inventors:
Xiaohong Quan - San Diego CA, US
Lennart K. Mathe - San Diego CA, US
Liang Dai - San Diego CA, US
Dinesh J. Alladi - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03K 7/08
H03K 5/156
US Classification:
455 76, 327176
Abstract:
All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Dc Offset Cancellation In A Direct-Conversion Receiver

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US Patent:
20050110550, May 26, 2005
Filed:
Nov 24, 2003
Appl. No.:
10/719833
Inventors:
Qian Shi - San Diego CA, US
Liang Dai - Carlsbad CA, US
Kevin Wang - San Diego CA, US
International Classification:
H03L005/00
US Classification:
327307000
Abstract:
The DCOC block is used in ZIF BB to form HPF function to cancel dc offset with a penalty of small silicon area and low power consumption. It is a LPF plus a voltage to current conversion (VIC) resistor, and can hook up with any BB opamp used in signal path, to form a feedback loop, with or without signal gain stages in the loop. The BB opamp is used as a summing point. The summing method is input current summing. The cutoff frequency of the HPF function is thus defined by the integrator, the VIC resistor, and the feedback resistor in the summing opamp. The presence of the VIC resistor can drastically reduce the integrator capacitor and resistor values and thus save silicon area or improve receiver performance.

Variable Rate Rc Calibration Circuit With Filter Cut-Off Frequency Programmability

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US Patent:
20050118980, Jun 2, 2005
Filed:
Dec 1, 2003
Appl. No.:
10/724415
Inventors:
Hung-Chuan Pai - San Diego CA, US
Liang Dai - Carlsbad CA, US
Kevin Wang - San Diego CA, US
Jie Huang - San Diego CA, US
International Classification:
H04B001/16
US Classification:
455340000
Abstract:
Two reference signals are applied to an RC calibration circuit, which utilizes programmable resistors and switched capacitor resistors in parallel at the inputs of a differential amplifier with feedback capacitors, for the first cycle and then the two reference signals are swapped for the successive cycle. The circuit inherent DC offset is cancelled by these two successive cycles. The time duration when the difference of the differential amplifier outputs in the calibration circuit starts to reverse ramping direction and the time when the difference crosses zero is counted in terms of reference clock cycles by a binary counter. The binary count is used to select the capacitance of the capacitor arrays in an RC filter for time constant calibration. This calibration circuit provides the flexibility for various reference clock rates by adjusting the programmable resistors. By tuning the same programmable resistors, this calibration circuit in addition provides the capability to changing the cut-off frequency of an RC filter circuit to another predetermined value.

Power Supply Generator With Noise Cancellation

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US Patent:
20120326686, Dec 27, 2012
Filed:
Jan 30, 2012
Appl. No.:
13/361785
Inventors:
Liang Dai - San Diego CA, US
Lennart Karl-Axel Mathe - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G05F 1/46
US Classification:
323283, 323282
Abstract:
Techniques for performing noise cancellation/attenuation are disclosed. In one design, an apparatus includes a power supply generator having a switcher, a coupling circuit, an envelope amplifier, and a feedback circuit. The switcher generates DC and low frequency components and the envelope amplifier generates high frequency components of a supply voltage for a load, e.g., a power amplifier. The switcher receives a first supply voltage and provides a switcher output signal having switcher noise. The coupling circuit receives the switcher output signal and provides a first output signal having a first version of the switcher noise. The feedback circuit receives the switcher output signal and provides a feedback signal. The envelope amplifier receives an envelope signal and the feedback signal and provides a second output signal having a second version of the switcher noise, which is used to attenuate the first version of the switcher noise at the load.

Low Distortion Feed-Forward Delta-Sigma Modulator

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US Patent:
20140035769, Feb 6, 2014
Filed:
Aug 2, 2012
Appl. No.:
13/565715
Inventors:
Omid Rajaee - San Diego CA, US
Liang Dai - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03M 3/00
US Classification:
341143
Abstract:
A low distortion feed forward delta sigma modulator includes a first adder configured to receive a feedback signal and an input signal. The modulator also includes a first integrator configured to receive an output from the first adder, and a second integrator configured to receive an output from the first integrator. The modulator further includes a second adder configured to receive a second integrated path from the second integrator, a first integrating path from the first integrator and a first summing path from the input signal. The modulator also has a last integrator configured to receive an output from the second adder.
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Liang Dai from San Diego, CA, age ~53 Get Report