Curtis H Stehley

8505015, Aug 6, 2013

Oct 29, 2009

12/608268

Curtis Stehley - Baltimore MD, US

Teradata US, Inc. - Dayton OH

G06F 9/46
G06F 9/40
G06F 7/38
G06F 13/00

718103, 718105, 718102, 718100, 712214, 712220, 711133

A “group work sorting” technique is used in a parallel computing system that executes multiple items of work across multiple parallel processing units, where each parallel processing unit processes one or more of the work items according to their positions in a prioritized work queue that corresponds to the parallel processing unit. When implementing the technique, one or more of the parallel processing units receives a new work item to be placed into a first work queue that corresponds to the parallel processing unit and receives data that indicates where one or more other parallel processing units would prefer to place the new work item in the prioritized work queues that correspond to the other parallel processing units. The parallel processing unit uses the received data as a guide in placing the new work item into the first work queue.

20080034054, Feb 7, 2008

Aug 7, 2006

11/462779

Curtis Stehley - Baltimore MD, US
Donald Pederson - San Diego CA, US

G06F 15/167

709213

A technique for use in managing message passing between processors within a database system involves providing a plurality of message buffers on each of those processors that are configured to send or receive messages, the number of buffers on each processor being less than the number of processors. A reservation list is also provided on each of those processors that are configured to send or receive messages.

59599944, Sep 28, 1999

Aug 19, 1996

8/699260

Gary Lee Boggs - Poway CA
Robert Samuel Cooper - Columbia SC
Gene Robert Erickson - Poway CA
Douglas Edward Hundley - Poway CA
Gregory H. Milby - San Marcos CA
P. Keith Muller - San Diego CA
Curtis Hall Stehley - San Diego CA
Donald G. Tipon - San Diego CA

NCR Corporation - Dayton OH

H04L 1256

370399

An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.

57686181, Jun 16, 1998

Dec 21, 1995

8/577678

Gene R. Erickson - Poway CA
Douglas E. Hundley - Poway CA
P. Keith Muller - San Diego CA
Curtis H. Stehley - San Diego CA

NCR Corporation - Dayton OH

G06F 1502

395829

A method of controlling an input/output (I/O) device connected to a computer to facilitate fast I/O data transfers. An address space for the I/O device is created in the virtual memory of the computer, wherein the address space comprises virtual registers that are used to directly control the I/O device. In essence, control registers and/or memory of the I/O device are mapped into the virtual address space, and the virtual address space is backed by control registers and/or memory on the I/O device. Thereafter, the I/O device detects writes to the address space. As a result, a pre-defined sequence of actions can be triggered in the I/O device by programming specified values into the data written into the mapped virtual address space.